问题标签 [system-generator]
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matlab - MATLAB 中的定点功能
当我使用 simulink 时，出现以下警告
并且定点功能对我的工作非常重要（使用系统生成器）
请，任何人都可以帮助我如何安装或将此功能添加到我的 MATLAB（R2013a）
matlab - Matlab系统生成器：黑盒错误
我在 Matlab 中使用 Xilinx 系统生成器块。
我只使用了一个带有网关输入和网关输出的黑匣子。
黑匣子的代码非常简单，可以在 ISE 设计套件中正常工作
但不幸的是，它不适用于 matlab 系统生成器。
我收到以下错误消息
谁能帮助我这段代码有什么问题以及我应该做些什么更改才能使模型正常工作
simulink - 在 Simulink/System Generator 中为黑匣子配置时钟信号
我使用代码 VHDL 通过 System Generator 的“黑匣子”在 Simulink 中制作一次性计时器。该模块得出的输入是：clk、en、触发器、延迟和输出是：pluse。现在我想使用 System Generator 在 Zynq 7020 上实现并使用时钟频率 = 1.562Mhz。我读了“ug897-vivado-system generator-user”，但我仍然不知道如何配置 clk。
Matlab/Simulink 中的图表
一次性定时器/黑盒的 VHDL 代码
Matlab 代码在导入 VHDL 代码时自动创建 https://drive.google.com/open?id=1jfztL-NgftDc7VAgAX4eHfuJF8uOgK3V
（对不起，我无法正确发布我的代码）
verilog - Sequential instatiation of Verilog Modules
I am trying to implement an algorithm on hardware(ZedBoard) which has multiple modules. There is a top module and I will instantiate all these multiple modules inside the top module.
Approximately there are 9 to 10 modules of which 3 has to run concurrently, rest has to run sequentially.
(I know that all modules inside the top module run concurrently. This is okay with the 3 modules that have to run concurrently but what about the rest of the modules that have to run sequentially???) and also ( I came to know that we can't instantiate modules inside always or initial block which actually doesn't make sense)
- Is there a way to instantiate modules so that they run sequentially(like one after the other)????
- Also, Is there a way to instantiate modules so that they run conditionally????
- Can this be achieved using the system generator????
fyi: I am using Verilog HDL and the code should be synthesizable