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I am trying to implement an algorithm on hardware(ZedBoard) which has multiple modules. There is a top module and I will instantiate all these multiple modules inside the top module.

Approximately there are 9 to 10 modules of which 3 has to run concurrently, rest has to run sequentially.

(I know that all modules inside the top module run concurrently. This is okay with the 3 modules that have to run concurrently but what about the rest of the modules that have to run sequentially???) and also ( I came to know that we can't instantiate modules inside always or initial block which actually doesn't make sense)

  1. Is there a way to instantiate modules so that they run sequentially(like one after the other)????
  2. Also, Is there a way to instantiate modules so that they run conditionally????
  3. Can this be achieved using the system generator????

fyi: I am using Verilog HDL and the code should be synthesizable

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Verilog 描述了硬件行为。所有硬件元素本质上都是平行的。因此，verilog 中的所有元素都以并行方式模拟以模拟硬件行为。

模型中的数据可以顺序或并行流动，具体取决于您的连接。如果您将数据应用到输入或元素，则该元素将处理数据并更新其输出。作为连接到第一个元素的输出的输入的元素将处理它们的输入并更新输出，依此类推。你可以把它想象成一个管道网。

为了在不同元素之间同步数据流，有时钟驱动触发器和锁存器。

基本上上面定义了你的verilog模型。

换句话说，verilog 因此不是一种常规的编程语言，

1) 安装模块只有一种方法：将它们连接到其他模块和内部电线。

2）没有办法有条件地运行或不运行模块。您可以拥有可以停止或重新路由数据流的硬件元素，例如多路复用器、锁存器等。幸运的是，行为 verilog 可以用“if”或“case”语句来描述那些。

3）你不能用任何发电机实现不可能的事情。

于 2018-11-04T23:36:57.263 回答