我正在尝试在 Xilinx 14.7 上运行 Spartan 3A 3400 视频入门套件的一些演示。提供的演示是使用 Xilinx 11.1 版本制作的。当我尝试在 14.7 中打开项目时，我在 mhs 文件中遇到了一些错误，这些错误在尝试后仍未解决。
我经常遇到的错误是
错误：EDK：4110 - IPNAME：mpmc，实例：mpmc_0 - 在任何存储库中都找不到 pcore 'mpmc_v4_06_a' 的 MPD - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 行389
警告：EDK：4088 - IPNAME：lmb_bram_if_cntlr，实例：ilmb_cntlr - 架构“spartan3adsp”的取代核心 - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 176 行
错误：EDK：4085 - IPNAME：xps_gpio，实例：LEDs_8Bit - MPD 中未找到参数 C_IS_BIDIR - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 212 行
错误：EDK:4085 - IPNAME：xps_gpio，实例：Push_Buttons_Position - 在 MPD 中找不到参数 C_IS_BIDIR - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 225 行
错误：EDK:4085 - IPNAME：xps_gpio，实例：DIP_Switches_8Bit - 在 MPD 中找不到端口 GPIO_in - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 243 行
错误：EDK:4085 - IPNAME：xps_gpio，实例：DIP_Switches_8Bit - 在 MPD 中找不到参数 C_IS_BIDIR - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 238 行
错误：EDK:4085 - IPNAME：mdm，实例：debug_module - 在 MPD 中找不到参数 C_UART_WIDTH - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 291 行
错误：EDK：4110 - IPNAME：mpmc，实例：mpmc_0 - 在任何存储库中都找不到 pcore 'mpmc_v4_06_a' 的 MPD - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 行389
错误：EDK：4111 - IPNAME：mpmc，实例：mpmc_0 - 找不到 pcore 的 MPD - C:\Users\DELL-PC\Downloads\ug4561\EDK_Demonstrations\Camera_Frame_Buffer_Demo\system.mhs 第 389 行
警告：EDK：3362 - 由于错误而无法打开项目。用本地文件 <E:/Xilinx14.7fullversion/14.7/ISE_DS/EDK/data/TextEditor.cfg> 覆盖 Xilinx 文件 <TextEditor.cfg>
这是我的 MHS 文件的文本
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Tue Sep 02 16:12:17 2008
# Target Board: Xilinx Spartan-3A DSP 3400A Development Board Rev D
# Family: spartan3adsp
# Device: xc3sd3400a
# Package: fg676
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 62.50 MHz
# On Chip Memory : 64 KB
# Total Off Chip Memory : 256 MB
# - DDR2_SDRAM = 256 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4]
PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin = fpga_0_DIP_Switches_8Bit_GPIO_in, DIR = I, VEC = [0:7]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [2:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n, DIR = IO, VEC = [3:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [31:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I, DIR = I
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O, DIR = O
PORT sys_clk_in_p = sys_clk_in_p, DIR = I, CLK_FREQ = 125000000
PORT sys_clk_in_n = sys_clk_in_n, DIR = I, CLK_FREQ = 125000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT video_out_scl = xps_iic_0_Scl, DIR = IO
PORT video_out_sda = xps_iic_0_Sda, DIR = IO
PORT dvi_out_reset_n = chrontel_rst, DIR = O, VEC = [0:0]
PORT fmc_card_scl = xps_iic_1_Scl, DIR = IO
PORT fmc_card_sda = xps_iic_1_Sda, DIR = IO
# DVI OUT Ports
PORT dvi_out_de = dvi_out_de, DIR = O
PORT dvi_out_vsync = dvi_out_vsync, DIR = O
PORT dvi_out_hsync = dvi_out_hsync, DIR = O
PORT dvi_out_data = dvi_out_data, VEC = [11:0], DIR = O
PORT dvi_out_clk_p = dvi_out_clk_p, DIR = O
PORT dvi_out_clk_n = dvi_out_clk_n, DIR = O
# DVI IN Ports
PORT dvi_in_de = dvi_in_de, DIR = I
PORT dvi_in_vsync = dvi_in_vsync, DIR = I
PORT dvi_in_hsync = dvi_in_hsync, DIR = I
PORT dvi_in_red = dvi_in_red, VEC = [7:0], DIR = I
PORT dvi_in_green = dvi_in_green, VEC = [7:0], DIR = I
PORT dvi_in_blue = dvi_in_blue, VEC = [7:0], DIR = I
# FMC-Video Ports
PORT vid_in_clk_p = vid_in_clk_p, DIR = I, VEC = [0:0]
PORT vid_in_clk_n = vid_in_clk_n, DIR = I, VEC = [0:0]
PORT display_clk_pin = display_clk, DIR = I, SIGIS = CLK, CLK_FREQ = 27000000, BUFFER_TYPE = BUFGP
PORT camera1_data = camera_0_data_i, DIR = I, VEC = [7:0]
PORT camera1_line_valid = camera_0_line_valid_i, DIR = I
PORT camera1_frame_valid = camera_0_frame_valid_i, DIR = I
BEGIN display_controller
PARAMETER INSTANCE = display_controller_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_SPLB_CLK_PERIOD_PS = 16000
PARAMETER C_DEFAULT_STRIDE = 0x00002000
PARAMETER C_DEFAULT_HSYNC = 0x10600030
PARAMETER C_DEFAULT_VSYNC_POL = 0x000a0221
PARAMETER C_DEFAULT_FRAME_SIZE = 0x028001e0
PARAMETER C_DEFAULT_FRAME0_BASEADDR = 0x10000000
PARAMETER C_BASEADDR = 0xcb400000
PARAMETER C_HIGHADDR = 0xcb40ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE DVI_VIDEO_OUT = display_controller_0_dvi_video_out
BUS_INTERFACE XIL_VFBC = display_controller_0_XIL_VFBC
PORT pixel_clk = pixel_clk
PORT ce = net_vcc
PORT display_clk = display_clk
PORT gray_frame_count = video_to_vfbc_0_GC_FRAME_COUNT
END
BEGIN video_to_vfbc
PARAMETER INSTANCE = video_to_vfbc_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_SPLB_CLK_PERIOD_PS = 16000
PARAMETER C_DEFAULT_FRAME0_BASEADDR = 0x10000000
PARAMETER C_DEFAULT_FRAME_ADDR_OFFSET = 0x0012c000
PARAMETER C_DEFAULT_MAX_FRAME_INDEX = 2
PARAMETER C_BASEADDR = 0xc0e00000
PARAMETER C_HIGHADDR = 0xc0e0ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE DVI_VIDEO_IN = gamma_plbw_0_DVI_VIDEO_OUT
BUS_INTERFACE XIL_VFBC = video_to_vfbc_0_XIL_VFBC
PORT IP_CLK = vid_in_clk
PORT DCM_LOCKED = dvi_clock_locked
PORT RESET = sys_bus_reset
PORT DDR_RDY = ddr_rdy
PORT GC_FRAME_COUNT = video_to_vfbc_0_GC_FRAME_COUNT
END
BEGIN microblaze
PARAMETER HW_VER = 8.50.c
PARAMETER INSTANCE = microblaze_0
PARAMETER C_FAMILY = spartan3adsp
PARAMETER C_USE_ICACHE = 1
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 2048
PARAMETER C_ICACHE_BASEADDR = 0x10000000
PARAMETER C_ICACHE_HIGHADDR = 0x1fffffff
PARAMETER C_DCACHE_BASEADDR = 0x10000000
PARAMETER C_DCACHE_HIGHADDR = 0x1fffffff
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_MSR_INSTR = 0
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER C_RESET_MSR = 0x000000a0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_INSTANCE = microblaze_0
PARAMETER C_CACHE_BYTE_SIZE = 2048
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE IXCL = microblaze_0_ixcl
BUS_INTERFACE DXCL = microblaze_0_dxcl
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER HW_VER = 1.02.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 62500000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_RX
PORT TX = fpga_0_RS232_Uart_TX
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 2.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END
BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons_Position
PARAMETER HW_VER = 2.00.a
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_8Bit
PARAMETER HW_VER = 2.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIP_Switches_8Bit_GPIO_in
END
BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.01.a
PARAMETER C_MEM_WIDTH = 16
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = mb_plb
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
PORT SysAce_Clk = fpga_0_SysACE_CompactFlash_SysACE_CLK
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 125000000
PARAMETER C_CLKOUT0_FREQ = 62500000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = GROUP0
PARAMETER C_CLKOUT3_FREQ = 125000000
PARAMETER C_CLKOUT3_PHASE = 90
PARAMETER C_CLKOUT3_GROUP = GROUP0
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT2 = DDR2_SDRAM_mpmc_clk_s
PORT CLKOUT3 = DDR2_SDRAM_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
# Core: mdm, Version:1.00.d is obsolete in EDK 11.1
# Revup has changed the mdm version to 1.00.e
PARAMETER HW_VER = 2.10.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
BUS_INTERFACE SPLB = mb_plb
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END
BEGIN xps_iic
PARAMETER INSTANCE = xps_iic_0
PARAMETER HW_VER = 2.03.a
PARAMETER C_CLK_FREQ = 62500000
PARAMETER C_BASEADDR = 0x81600000
PARAMETER C_HIGHADDR = 0x8160ffff
BUS_INTERFACE SPLB = mb_plb
PORT Scl = xps_iic_0_Scl
PORT Sda = xps_iic_0_Sda
PORT Gpo = chrontel_rst
END
BEGIN xps_iic
PARAMETER INSTANCE = xps_iic_1
PARAMETER HW_VER = 2.03.a
PARAMETER C_CLK_FREQ = 62500000
PARAMETER C_BASEADDR = 0x81620000
PARAMETER C_HIGHADDR = 0x8162ffff
PARAMETER C_GPO_WIDTH = 2
BUS_INTERFACE SPLB = mb_plb
PORT Scl = xps_iic_1_Scl
PORT Sda = xps_iic_1_Sda
PORT Gpo = dvi_in_mode & dcm_0_rst
END
BEGIN dvi_out
PARAMETER INSTANCE = dvi_out_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE DVI_VIDEO_IN = display_controller_0_dvi_video_out
PORT clk = pixel_clk
PORT ce = net_vcc
PORT de = dvi_out_de
PORT vsync = dvi_out_vsync
PORT hsync = dvi_out_hsync
PORT dvi_data = dvi_out_data
PORT dvi_clk_p = dvi_out_clk_p
PORT dvi_clk_n = dvi_out_clk_n
PORT reset_n = net_vcc
END
BEGIN util_ds_buf
PARAMETER INSTANCE = util_ds_buf_1
PARAMETER HW_VER = 1.01.a
PARAMETER C_BUF_TYPE = IBUFDS
PORT IBUF_DS_N = vid_in_clk_n
PORT IBUF_DS_P = vid_in_clk_p
PORT IBUF_OUT = vid_in_clk_dcm
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_module_0
PARAMETER HW_VER = 1.00.e
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 35.000
PORT CLKIN = vid_in_clk_dcm
PORT RST = dcm_0_rst
PORT CLKFB = vid_in_clk
PORT CLK0 = vid_in_clk
PORT LOCKED = dvi_clock_locked
END
BEGIN util_ds_buf
PARAMETER INSTANCE = util_ds_buf_0
PARAMETER HW_VER = 1.01.a
PORT IBUF_DS_N = sys_clk_in_n
PORT IBUF_DS_P = sys_clk_in_p
PORT IBUF_OUT = dcm_clk_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = not
PARAMETER C_SIZE = 1
PORT Op1 = dvi_clock_locked
PORT Op2 = net_gnd
END
BEGIN mpmc
PARAMETER INSTANCE = mpmc_0
PARAMETER HW_VER = 4.06.a
PARAMETER C_MEM_PARTNO = MT4HTF6464H-667
PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_PIM1_BASETYPE = 1
PARAMETER C_PIM2_BASETYPE = 6
PARAMETER C_PIM3_BASETYPE = 6
PARAMETER C_NUM_PORTS = 4
PARAMETER C_MPMC_BASEADDR = 0x10000000
PARAMETER C_MPMC_HIGHADDR = 0x1fffffff
BUS_INTERFACE XCL0 = microblaze_0_ixcl
BUS_INTERFACE XCL1 = microblaze_0_dxcl
BUS_INTERFACE VFBC3 = display_controller_0_XIL_VFBC
BUS_INTERFACE VFBC2 = video_to_vfbc_0_XIL_VFBC
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n
PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS
PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n
PORT DDR2_DQS_Div_I = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I
PORT DDR2_DQS_Div_O = fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O
PORT MPMC_Rst = sys_bus_reset
PORT MPMC_InitDone = ddr_rdy
PORT MPMC_Clk0 = DDR2_SDRAM_mpmc_clk_s
PORT MPMC_Clk90 = DDR2_SDRAM_mpmc_clk_90_s
END
BEGIN camera
PARAMETER INSTANCE = camera_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE CAMERA_VIDEO_OUT = camera_0_CAMERA_VIDEO_OUT
PORT data_i = camera_0_data_i
PORT line_valid_i = camera_0_line_valid_i
PORT frame_valid_i = camera_0_frame_valid_i
PORT ce = net_vcc
PORT clk = vid_in_clk
END
BEGIN vsk_camera_vop_plbw
PARAMETER INSTANCE = vsk_camera_vop_plbw_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xc9e00000
PARAMETER C_HIGHADDR = 0xc9e0ffff
BUS_INTERFACE CAMERA_VIDEO_IN = camera_0_CAMERA_VIDEO_OUT
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE DVI_VIDEO_OUT = vsk_camera_vop_plbw_0_DVI_VIDEO_OUT
PORT sysgen_clk = vid_in_clk
END
BEGIN gamma_plbw
PARAMETER INSTANCE = gamma_plbw_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xcc600000
PARAMETER C_HIGHADDR = 0xcc60ffff
BUS_INTERFACE DVI_VIDEO_IN = vsk_camera_vop_plbw_0_DVI_VIDEO_OUT
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE DVI_VIDEO_OUT = gamma_plbw_0_DVI_VIDEO_OUT
PORT sysgen_clk = vid_in_clk
END