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我正在尝试将板载差分时钟用于我的 verilog 代码。以下是我的 verilog 和约束文件的片段。即使代码合成得很好，我也看不到板上的 LED 变化。有人可以告诉我我在这里缺少什么吗？

验证：

module leds(
    input DIFF_SYS_P,
    input DIFF_SYS_N,
    output reg [7:0] leds=8'd0,
    output clk
    );

    reg [31:0] count =0;
    wire clk;



    IBUFGDS #(
    .DIFF_TERM("FALSE"),
    .IBUF_LOW_PWR("TRUE"),
    .IOSTANDARD("DEFAULT")
    ) IBUFGDS_inst (
       .O(clk),
        .I(DIFF_SYS_P),
        .IB(DIFF_SYS_N)
        );


    always@(posedge clk) begin 
      if(count ==10) begin
        leds <= 8'b10101010;
        count <=count +1;
       end

       else begin
       count<=count +1; 
     end
  end
endmodule

约束（xdc）：

set_property PACKAGE_PIN G18 [get_ports DIFF_SYS_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DIFF_SYS_N]
set_property PACKAGE_PIN H19 [get_ports DIFF_SYS_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DIFF_SYS_P]
set_property PACKAGE_PIN AM39 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[0]}]
set_property PACKAGE_PIN AN39 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[1]}]
set_property PACKAGE_PIN AR37 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[2]}]
set_property PACKAGE_PIN AT37 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[3]}]
set_property PACKAGE_PIN AR35 [get_ports {leds[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[4]}]
set_property PACKAGE_PIN AP41 [get_ports {leds[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[5]}]
set_property PACKAGE_PIN AP42 [get_ports {leds[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[6]}]
set_property PACKAGE_PIN AU39 [get_ports {leds[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {leds[7]}]
create_clock -period 5.000 -name DIFF_SYS_P -waveform {0.000 2.500} [get_ports DIFF_SYS_P]**
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1 回答 1

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首先，您可能希望使用 IBUFG 跟踪您的 IBUFGDS，以便将时钟实际添加到全局时钟网络上。之后，您将需要除以 10 以上的 LOT 才能看到任何闪烁。我建议数到 1 亿，重置计数器，并切换 LED，而不是仅仅设置它们。

于 2018-06-06T09:04:56.597 回答