我想创建一个足够灵活的地址解码器,以便在更改选择器和解码输出信号的位数时使用。
因此,不要使用看起来像这样的静态(固定输入/输出大小)解码器:
entity Address_Decoder is
Generic
(
C_INPUT_SIZE: integer := 2
);
Port
(
input : in STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
output : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end Address_Decoder;
architecture Behavioral of Address_Decoder is
begin
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
output <= "0000";
else
case <input> is
when "00" => <output> <= "0001";
when "01" => <output> <= "0010";
when "10" => <output> <= "0100";
when "11" => <output> <= "1000";
when others => <output> <= "0000";
end case;
end if;
end if;
end process;
end Behavioral;
有一些更灵活/通用的东西,看起来像这样:
entity Address_Decoder is
Generic
(
C_INPUT_SIZE: integer := 2
);
Port
(
input : in STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
output : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end Address_Decoder;
architecture Behavioral of Address_Decoder is
begin
DECODE_PROC:
process (clk)
begin
if(rising_edge(clk)) then
if ( rst = '1') then
output <= conv_std_logic_vector(0, output'length);
else
case (input) is
for i in 0 to (2**C_INPUT_SIZE)-1 generate
begin
when (i = conv_integer(input)) => output <= conv_std_logic_vector((i*2), output'length);
end generate;
when others => output <= conv_std_logic_vector(0, output'length);
end case;
end if;
end if;
end process;
end Behavioral;
我知道这段代码无效,并且“何时”测试用例必须是常量,并且我不能像这样在 case 语句之间使用 for-generate,但它显示了我所追求的是什么:一个实体足够聪明,可以满足我的需求。
我一直试图为这个问题找到一个优雅的解决方案,但没有取得多大成功,所以,我愿意接受任何建议。
在此先感谢,埃里克