我正在尝试添加两个存储符号位的寄存器,其中一个是 3 位 [ FRQ(2 downto 0)
],另一个是 7 位 [ PHS(6 downto 0)
] ...并且必须将这两个寄存器的加法存储在 7 位寄存器 [ PHS(6 downto 0)
] 中。提前感谢您的帮助。
我得到的错误是..>>> 错误:/..integrator.vhd(47): near "process": (vcom-1576) Expecting IF VHDL
这是我的代码:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity integ is
port (
SMP_CLK : in std_logic;
RESET : in std_logic;
PHS : out signed (6 downto 0);
FRQ : in signed (2 downto 0)
);
end integ;
architecture behaviour of integ is
signal sig_FRQ : signed(2 downto 0) := (others => '0');
signal ext_FRQ : signed(6 downto 0) := (others => '0');
signal sig_PHS : signed(6 downto 0) := (others => '0');
signal temp_PHS : signed(6 downto 0) := (others => '0');
begin
sig_FRQ <=FRQ;
temp_PHS <= sig_PHS;
--PHS <=signal_PHS;
process (SMP_CLK, RESET)
begin
if sig_FRQ(2)='1' then
ext_FRQ(6 downto 3) <= b"0000";
else
ext_FRQ(6 downto 3) <= b"1111";
--end if;
if RESET='1' then
sig_PHS <= b"0000000";
elsif (rising_edge(SMP_CLK) ) then
-- temp_PHS <= sig_PHS;
sig_PHS <= signed(ext_FRQ) + signed(temp_PHS);
end process;
sig_PHS => PHS;
end behaviour;