我正在尝试使用 verilog 在我的 baysis2 FGPA 上创建一个简单的 4 位密码系统。我想使用 7 段显示器来显示输入的数字(将使用键盘输入)。现在我只是在测试以确保输入正确的数字。问题是,七段显示器的第一个数字不亮,而其他所有数字都亮。我已经在多个板上进行了尝试,并且所有其他由同一根电线启用的数字都很好。为什么会这样?
module enter_password(
input wire clk, reset,
input wire ps2d, ps2c, rx_en,
output wire [6:0] seven_seg_display,
output wire assert_seg);
wire [7:0] scan_out;
wire [7:0] ascii_code;
//initial seven_seg_display = 7'b0000000;
assign assert_seg = 1'b1;
// instantiate ps2 receiver
ps2_rx ps2_rx_unit(
.clk(clk), .reset(reset), .rx_en(1'b1),
.ps2d(ps2d), .ps2c(ps2c),
.rx_done_tick(scan_done_tick), .dout(scan_out));
// instantiate key-to-ascii code conversion circuit
Scan_to_ascii key2ascii(.key_code(scan_out), .ascii_code(ascii_code));
assign seven_seg_display =
ascii_code == 8'h30 ? 7'b0000001: //0
ascii_code == 8'h31 ? 7'b1001111: //1
ascii_code == 8'h32 ? 7'b0010010: //2
ascii_code == 8'h33 ? 7'b0000110: //3
ascii_code == 8'h34 ? 7'b1001100: //4
ascii_code == 8'h35 ? 7'b0100100: //5
ascii_code == 8'h36 ? 7'b0100000: //6
ascii_code == 8'h37 ? 7'b0001111: //7
ascii_code == 8'h38 ? 7'b0000000: //8
ascii_code == 8'h39 ? 7'b0000100: //9
7'b1111111; //e for error 0
endmodule
ucf
NET "seven_seg_display[6]" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seven_seg_display[5]" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seven_seg_display[4]" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seven_seg_display[3]" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seven_seg_display[2]" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seven_seg_display[1]" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seven_seg_display[0]" LOC = "M12"; # Bank = 1, Signal name = CG
#NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP
NET "assert_seg" LOC = "K14"; # Bank = 1, Signal name = AN3
NET "assert_seg" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "assert_seg" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "assert_seg" LOC = "F12"; # Bank = 1, Signal name = AN0