我正在尝试为 Spartan-S6 系列 FPGA 使用 VHDL 流程制作 DNA 阅读器模块。问题是我的代码无法合成。它适用于模拟，但在合成时它只是卡住了。我还用谷歌搜索了不可合成的 VHDL 进程，但我认为我做得对，它必须被很好地合成。这是我的流程代码：
FSMOutputController:process(state,readDnaCmd)
variable clkCounter :unsigned(7 downto 0) := "00000000";
begin
case state is
when zeroState =>
if readDnaCmd = '1' then
DNA_Read <= '1';
SR_read <= '0';
else
SR_read <= '1';
end if;
when initState =>
DNA_Read <= '0';
SR_read <= '1';
SR_clk <= DNA_CLK_temp;
DNA_Shift <= '1';
when endReadState =>
DNA_shift <= '0';
SR_read <= '0';
when readState =>
clkCounter := clkCounter + 1;
--clkCounter2 <= clkCounter2 + X"01";
SR_read <= '0';
end case;
end process FSMOutputController;
这是尝试合成时 ISE 日志的一部分：
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <testDNALock>.
Related source file is "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd".
WARNING:Xst:647 - Input <CLK_98MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'DNAVerify', unconnected in block 'testDNALock', is tied to its initial value (0).
Summary:
no macro.
Unit <testDNALock> synthesized.
并且它卡在这里并且不用于包含我的进程的我的 DNALock 文件。还有另一件事：当我注释掉分配行时，它将被正确合成：
FSMOutputController:process(state,readDnaCmd)
variable clkCounter :unsigned(7 downto 0) := "00000000";
begin
case state is
when zeroState =>
if readDnaCmd = '1' then
--DNA_Read <= '1';
--SR_read <= '0';
else
--SR_read <= '1';
end if;
when initState =>
--DNA_Read <= '0';
--SR_read <= '1';
--SR_clk <= DNA_CLK_temp;
--DNA_Shift <= '1';
when endReadState =>
-- DNA_shift <= '0';
-- SR_read <= '0';
when readState =>
clkCounter := clkCounter + 1;
--clkCounter2 <= clkCounter2 + X"01";
-- SR_read <= '0';
end case;
end process FSMOutputController;
那么报告将是：
=========================================================================
* Design Summary *
=========================================================================
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
=========================================================================
Process "Synthesize - XST" completed successfully