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Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.

Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found".

Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" : mm_slave."

I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.

So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?

I have some ideas but don't like them:

  1. Add MM-Slave for each irq (it looks like waste of resources).

  2. Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do? I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.

  3. Merge all interrupts into one wire (they all will share the same priority).

  4. Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers. After Component Editor stage is finished Qsys doesn't accept such a system.

Please help.

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最后，我发现了以下内容：

A. 如果您在一个自定义 Qsys 模块中需要多个 IRQ 发送器，则每个模块需要一个 MM-Slave。从 GUI 组织看来，您似乎正在将 MM-Slave 分配给 IRQ，但是（据我所知）它的工作方式直接相反：IRQ 与 MM-Slave 相关联，并且它最多可能有一个 IRQ。我没有尝试实际运行它，但 BSP 文件看起来是正确的，并且至少所有内容都可以编译。我希望，有（或将会有）更好的方法来实现这一目标。

B. 如果您可以在所有中断之间共享相同的优先级，那么您可以通过仅使用 1 个中断发送器从而仅使用 1 个 MM-Slave 来避免该问题。它在开发板上工作。

于 2015-10-09T11:24:51.480 回答