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我在 Xilinx ISE IDE 上并使用原理图编辑器。

示意图 （点击打开新窗口）

约束文件如下：

NET "A" LOC = M18;
NET "F" LOC = P15;
NET "B" LOC = M16;


NET "A" PULLUP;
NET "B" PULLUP;
NET "F" DRIVE = 8;

但是当我想编译我的程序时，出现了这个错误：

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <B> is placed at site <M16>. The corresponding BUFG component
   <B_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
   of IOBs that can use the fast path to the Clocker buffer, and they are not
   being used. You may want to analyze why this problem exists and correct it.
   If this sub optimal condition is acceptable for this design, you may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING and allow your design to continue. However, the use of this override
   is highly discouraged as it may lead to very poor timing results. It is
   recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to override this clock rule.
   < NET "B" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

如何解决？

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1 回答 1

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虽然理论上任何信号都可以用作时钟，但 FPGA 并非如此。至少不是最佳的。时钟需要特殊考虑，以限制 FPGA 的哪个引脚可以路由到时钟网络。

我怀疑在您的情况下，您使用了一个按钮作为时钟信号，由于去抖动以及它不是启用时钟的输入端口这一事实，它仅适用于非常小的设计（如您的设计）。

您可以通过将以下约束添加到 .ucf 来告诉工具您想要次优且可能错误的时钟路径：

NET "B" CLOCK_DEDICATED_ROUTE = FALSE;

请记住，您不应该在不确定您的设计是否正常的情况下这样做......我建议您使用连接到 FPGA 上的时钟端口的“真实”时钟进行进一步设计，每块板都有一个。该约束将使您的设计工作，但在更大、更快的设计中可能会成为问题的根源。

于 2015-07-19T13:37:04.417 回答