我想我在 VHDL 中有一些设计问题。
我正在尝试将一些引脚设置为高低。设置另一个连接的板。
我收到以下警告：
[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_PORB_IBUF' at site B5, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:137]
[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_SRSTB_IBUF' at site C9, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:138]
[Constraints 18-5] Cannot loc instance 'processing_system7_0_PS_CLK_IBUF' at site F7, Site location is not valid [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/implementation/module_1_processing_system7_0_wrapper.ncf:139]
[Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_uart_out_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_uart_out_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:5]
[Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site J15, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:5]
[Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_te_485_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_GND' driving the net 'module_1_i/receiver_0_rs_te_485_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:6]
[Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_GND' at site J16, Unknown instance type 'GND' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:6]
[Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_hf_out_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_hf_out_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:7]
[Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site L17, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:7]
[Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_rxen_bar_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_GND' driving the net 'module_1_i/receiver_0_rs_rxen_bar_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:8]
[Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_GND' at site N17, Unknown instance type 'GND' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:8]
[Designutils 20-1397] We found multiple IO primitives connected to net 'module_1_i/receiver_0_rs_dxen_pin'. It is ambiguous to apply a single loc constraint on multiple IO primitives; we will keep the constraint on the instance 'module_1_i/receiver_0/XST_VCC' driving the net 'module_1_i/receiver_0_rs_dxen_pin'. [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:9]
[Constraints 18-5] Cannot loc instance 'module_1_i/receiver_0/XST_VCC' at site M15, Unknown instance type 'VCC' [D:/Sensor/receiver/receiver.srcs/sources_1/edk/module_1/data/module_1.ncf:9]
导致这些警告的代码部分可能是：我在 EDK 项目中有一个 IP：它有两个文件：reciever.vhd 和 user_logic.vh。在 user_logic.vhd 中，我制作了一些端口，并尝试为这些端口分配高值和低值。
entity user_logic is
port
(
rs_rx : in std_logic;
rs_clk_in : in std_logic;
rs_dxen : out std_logic;
rs_uart_out : out std_logic;
rs_hf_out : out std_logic;
rs_rxen_bar : out std_logic;
rs_te_485 : out std_logic;
Bus2IP_Resetn : in std_logic;
);
architecture IMP of user_logic is
signal q : unsigned(9 downto 0) := (others => '0');
signal rx_clk : std_logic := '0' ;
signal rs_dxen_i : std_logic;
signal rs_uart_out_i : std_logic;
signal rs_hf_out_i : std_logic;
signal rs_rxen_bar_i : std_logic;
signal rs_te_485_i : std_logic;
begin
rs_dxen <= rs_dxen_i;
rs_uart_out <= rs_uart_out_i;
rs_hf_out <= rs_hf_out_i;
rs_rxen_bar <= rs_rxen_bar_i;
rs_te_485 <= rs_te_485_i;
process ( Bus2IP_Resetn, rs_clk_in ) is
begin
if(Bus2IP_Resetn = '1') then
rs_dxen_i <= '1';
rs_uart_out_i <= '1';
rs_hf_out_i <= '1';
rs_rxen_bar_i <= '0';
rs_te_485_i <= '0';
elsif rs_clk_in'event and rs_clk_in = '1' then
q <= q + 1;
rx_clk <= q(9); --- 58.gdfg/2^9=~ 115.82Khz baud rate = 115200
end if;
end process;
我将这些端口设为外部端口并连接到一些引脚。但是我收到了上面提到的警告，我无法将相应的引脚设置为高和低。但是，如果在代码中我没有为输出端口分配任何值，则不会出现警告。
B5、C9 和 F7 的警告可以忽略。三警告总是来的。如果我没有在开始后放置这部分，则不会出现另一个警告： rs_dxen <= rs_dxen_i; rs_uart_out <= rs_uart_out_i; rs_hf_out <= rs_hf_out_i; rs_rxen_bar <= rs_rxen_bar_i; rs_te_485 <= rs_te_485_i;