在用 VHDL 测试一个简单的生命游戏实现时,空测试台的 GHDL 模拟在打印出“测试结束”消息后以 100% 的 CPU 使用率挂起。
这是代码:
----- Package ------------------------------
library ieee;
use ieee.std_logic_1164.all;
package data_types is
type array2D is array (0 to 10, 0 to 10) of std_logic;
end data_types;
----- Main Code ----------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.data_types.all;
entity de0 is
port (matrix : inout array2D);
end de0;
architecture life of de0 is
-- Return the integer value of a cell, treating all out of bounds as 0
function cellValue (matrix : array2D; x, y : integer) return integer is
begin
if (y < 0 or y > matrix'high(1) or x < 0 or x > matrix'high(2) or matrix(y, x) = '0') then
return 0;
else
return 1;
end if;
end cellValue;
begin
-- Iterate over all cells
row: for y in matrix'range(1) generate
column: for x in matrix'range(2) generate
process
variable neighbours : integer := cellValue(matrix, x - 1, y - 1) +
cellValue(matrix, x - 1, y) +
cellValue(matrix, x - 1, y + 1) +
cellValue(matrix, x, y - 1) +
cellValue(matrix, x, y + 1) +
cellValue(matrix, x + 1, y - 1) +
cellValue(matrix, x + 1, y) +
cellValue(matrix, x + 1, y + 1);
begin
-- Update the cell value according to the game of life rules
if (neighbours = 2 or neighbours = 3) then
matrix(y, x) <= '1';
else
matrix(y, x) <= '0';
end if;
end process;
end generate;
end generate;
end life;
和测试台:
library ieee;
use ieee.std_logic_1164.all;
use work.data_types.all;
entity life_tb is
end life_tb;
architecture behaviour of life_tb is
component life
port (matrix : inout array2D);
end component;
for test: life use entity work.de0;
signal matrix : array2D;
begin
test: life port map (matrix => matrix);
process
begin
assert false
report "End of test" severity note;
wait;
end process;
end behaviour;