我的编译器给了我这些错误:
# 错误:COMP96_0305: SUBONE_MODULE_VHDL.vhd : (93, 23): 找不到这些实际值的函数“TO_INTEGER”。
# Error: COMP96_0138: SUBONE_MODULE_VHDL.vhd : (93, 23): 数组对象引用中的索引类型与其范围类型不兼容。**
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SUBONE_MODULE_VHDL is
port(
addr : in STD_LOGIC_VECTOR(4 downto 0);
clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(4 downto 0)
);
end SUBONE_MODULE_VHDL;
architecture SUBONE_MODULE_VHDL of SUBONE_MODULE_VHDL is
type ROM_Array is array (0 to 31)
of std_logic_vector(4 downto 0);
constant Content: ROM_Array := (
0 => "10011", -- Suppose ROM has
1 => "00000", -- prestored value
2 => "00001", -- like this table
3 => "00010", --
4 => "00011", --
5 => "00100", --
6 => "00101", --
7 => "00110", --
8 => "00111", --
9 => "01000", --
10 => "01001", --
11 => "01010", --
12 => "01011", --
13 => "01100", --
14 => "01101", --
15 => "01110", --
16 => "01111", --
17 => "01110", --
18 => "01110", --
19 => "01110", --
20 => "01110", --
21 => "00000", --
22 => "00001", --
23 => "00010", --
24 => "00011", --
25 => "00100", --
26 => "00101", --
27 => "00110", --
28 => "00111", --
29 => "01000", --
30 => "01001", --
31 => "01010", --
OTHERS => "00000"
);
begin
process(clk, addr)
variable addr : integer := 0;
begin
if( clk'event and clk = '1' ) then
dout <= Content(TO_INTEGER(addr));
end if;
end process;
end SUBONE_MODULE_VHDL;