library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;
entity sobel is
port (
top_left_pixel : in std_logic;
top_middle_pixel : in std_logic;
top_right_pixel : in std_logic;
middle_left_pixel : in std_logic;
middle_right_pixel : in std_logic;
bottom_left_pixel : in std_logic;
bottom_middle_pixel : in std_logic;
bottom_right_pixel : in std_logic;
sobelx : out std_logic;
sobely : out std_logic
);
end entity sobel;
architecture noddy of sobel is
signal p1 : std_logic := top_left_pixel;
signal p2 : std_logic := top_middle_pixel;
signal p3 : std_logic := top_right_pixel;
signal p4 : std_logic := middle_left_pixel;
signal p6 : std_logic := middle_right_pixel;
signal p7 : std_logic := bottom_left_pixel;
signal p8 : std_logic := bottom_middle_pixel;
signal p9 : std_logic := bottom_right_pixel;
signal sobelx_s : integer;
signal sobely_s : integer;
begin
-- Same error on both these lines
sobelx_s <= (p3 - p1) + ((p6 & '0') - (p4 & '0')) + (p9 - p7);
sobely_s <= (bottom_left_pixel - top_left_pixel) + ((bottom_middle_pixel & '0') - (top_middle_pixel & '0')) + (bottom_right_pixel - top_right_pixel);
end architecture noddy;
我正在尝试用很少的经验用 VHDL 构建一个 sobel 滤波器。该实体仅用于在测试台上进行尝试,以查看 sobel 算法是否适用于输入数据。
有什么建议么?
非常感谢所有答案,如果您可以将完整的 VHDL 初学者引导到有用的东西,不客气