这是代码，这是在nexys4上实现PicoBlaze的代码。使用此代码，我们希望使用八个开关打开和关闭 fpga 的八个 LED
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity kcpsm6_final is
Port ( clk : in STD_LOGIC;
Leds : out STD_LOGIC_VECTOR (7 downto 0);
sw : in STD_LOGIC_VECTOR (7 downto 0));
end kcpsm6_final;
architecture Behavioral of kcpsm6_final is
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := x"00";
interrupt_vector : std_logic_vector(11 downto 0) := x"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component led
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
begin
-- programming of processor
program_rom: led -- name to match your psm file
generic map( C_FAMILY => "S6", -- family 's6', 'v6', or '7s'
C_RAM_SIZE_KWORDS => 1, -- program size '1', '2', or '4'
C_JTAG_LOADER_ENABLE => 0) -- include jtag jtag loader when set to '1'
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => kcpsm6_reset,
clk => clk);
-- processor
processor: kcpsm6
generic map( hwbuild => x"00",
interrupt_vector => x"3FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(0) is
when '0' => in_port <= sw;
所以在这里我们遇到了字符“x”的错误，我们正在寻找解决方案，但这些解决方案都不能帮助我们修复它。
when others => in_port <= "xxxxxxxx";
end case;
end if;
end process input_ports;
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe = '1' then
if port_id(0) = '1' then
Leds <= out_port;
end if;
end if;
end if;
end process output_ports;
end Behavioral;
我收到以下错误
ERROR:HDLCompiler:304 - "C:\ProyectosVHDL\Pico_work\kcpsm6_final.vhd" Line 126: Character 'x' is not in element type std_logic
ERROR:HDLCompiler:854 - "C:\ProyectosVHDL\Pico_work\kcpsm6_final.vhd" Line 37: Unit <behavioral> ignored due to previous errors.
我不知道如何解决它，请我需要帮助。