我刚刚在 Xilinx 中创建了一个自定义 IP，它生成了一个我在 Verilog 中需要的 user_logic 文件，但是我在更改代码时遇到了问题。
我需要的是实现数据进入 FSL 执行一些添加，然后将值返回给 MicroBlaze，正在发送数据但现在正在返回。
enter code here
//----------------------------------------------------------------------------
// video - module
//----------------------------------------------------------------------------
// IMPORTANT:
// DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
//
// SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
//
// TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
// PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
// OF THE USER_LOGIC ENTITY.
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: video
// Version: 1.00.a
// Description: Example FSL core (Verilog).
// Date: Tue Jul 12 10:03:57 2011 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
//
//
// Definition of Ports
// FSL_Clk : Synchronous clock
// FSL_Rst : System reset, should always come from FSL bus
// FSL_S_Clk : Slave asynchronous clock
// FSL_S_Read : Read signal, requiring next available input to be read
// FSL_S_Data : Input data
// FSL_S_Control : Control Bit, indicating the input data are control word
// FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
// FSL_M_Clk : Master asynchronous clock
// FSL_M_Write : Write signal, enabling writing to output FSL bus
// FSL_M_Data : Output data
// FSL_M_Control : Control Bit, indicating the output data are contol word
// FSL_M_Full : Full Bit, indicating output FSL bus is full
//
////////////////////////////////////////////////////////////////////////////////
//----------------------------------------
// Module Section
//----------------------------------------
module video
(
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
// DO NOT EDIT BELOW THIS LINE ////////////////////
// Bus protocol ports, do not add or delete.
FSL_Clk,
FSL_Rst,
FSL_S_Clk,
FSL_S_Read,
FSL_S_Data,
FSL_S_Control,
FSL_S_Exists,
FSL_M_Clk,
FSL_M_Write,
FSL_M_Data,
FSL_M_Control,
FSL_M_Full
// DO NOT EDIT ABOVE THIS LINE ////////////////////
);
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
input FSL_Clk;
input FSL_Rst;
output FSL_S_Clk;
output FSL_S_Read;
input [0 : 31] FSL_S_Data;
input FSL_S_Control;
input FSL_S_Exists;
output FSL_M_Clk;
output FSL_M_Write;
output [0 : 31] FSL_M_Data;
output FSL_M_Control;
input FSL_M_Full;
// ADD USER PARAMETERS BELOW THIS LINE
// --USER parameters added here
// ADD USER PARAMETERS ABOVE THIS LINE
//----------------------------------------
// Implementation Section
//----------------------------------------
// In this section, we povide an example implementation of MODULE video
// that does the following:
//
// 1. Read all inputs
// 2. Add each input to the contents of register 'sum' which
// acts as an accumulator
// 3. After all the inputs have been read, write out the
// content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times
//
// You will need to modify this example for
// MODULE video to implement your coprocessor
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 64;
// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 64;
// Define the states of state machine
localparam Idle = 3'b100;
localparam Read_Inputs = 3'b010;
localparam Write_Outputs = 3'b001;
reg [0:2] state;
// Accumulator to hold sum of inputs read at any point in time
reg [0:31] sum;
// Counters to store the number inputs read & outputs written
reg [0:NUMBER_OF_INPUT_WORDS - 1] nr_of_reads;
reg [0:NUMBER_OF_OUTPUT_WORDS - 1] nr_of_writes;
// CAUTION:
// The sequence in which data are read in should be
// consistent with the sequence they are written in the
// driver's video.c file
assign FSL_S_Read = (state == Read_Inputs) ? FSL_S_Exists : 0;
assign FSL_M_Write = (state == Write_Outputs) ? ~FSL_M_Full : 0;
assign FSL_M_Data = sum;
always @(posedge FSL_Clk)
begin // process The_SW_accelerator
if (FSL_Rst) // Synchronous reset (active high)
begin
// CAUTION: make sure your reset polarity is consistent with the
// system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= 0;
end
else
case (state)
Idle:
if (FSL_S_Exists == 1)
begin
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= 0;
end
Read_Inputs:
if (FSL_S_Exists == 1)
begin
// Coprocessor function (Adding) happens here
sum <= sum + FSL_S_Data;
if (nr_of_reads == 0)
begin
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
end
else
nr_of_reads <= nr_of_reads - 1;
end
Write_Outputs:
if (nr_of_writes == 0)
state <= Idle;
else
if (FSL_M_Full == 0) nr_of_writes <= nr_of_writes - 1;
endcase
end
endmodule