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我是 VHDL 新手，有简单的错误。

基本上我有 4 个二进制输入和 3 个二进制输出。条件很简单，如果在所有 4 个输入中我只有一个“1”，则输出 l3 接收“1”而其他“0”，如果我有两个“1”，则输出 l2 接收“1”和太多“ 0'，如果我有两个以上的'1'，则输出 l1 接收'1'，其他的接收'0'。

基本上 J1、J2、J3 和 J4 是输入。L1、L2 和 L3 是输出。你可以验证真值表。

我正在尝试用 EDA Playground ( https://www.edaplayground.com/ )中的代码解决这个问题

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SistemaVotacion IS
PORT (j1, j2, j3, j4: IN std_logic;
      l1, l2, l3: OUT std_logic);
END SistemaVotacion;

ARCHITECTURE SistemaArchitecture OF SistemaVotacion IS
BEGIN
    l1 <= '1' WHEN (j1 = '0' and j2 = '1' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '1' and j4 = '1')
    ELSE '0';
    l2 <= '1' WHEN (j1 = '0' and j2 = '0' and j3 = '1' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '1' and j3 = '0' and j4 = '0')
    ELSE '0';
    l3 => '1' WHEN (j1 = '0' and j2 = '0' and j3 = '0' and j4 = '0')
    ELSE '1' WHEN (j1 = '0' and j2 = '0' and j3 = '0' and j4 = '1')
    ELSE '1' WHEN (j1 = '0' and j2 = '0' and j3 = '1' and j4 = '0')
    ELSE '1' WHEN (j1 = '0' and j2 = '1' and j3 = '0' and j4 = '0')
    ELSE '1' WHEN (j1 = '1' and j2 = '0' and j3 = '0' and j4 = '0')
    ELSE '0';
END SistemaArchitecture;

但是我遇到了很多错误，例如：

  1. COMP96 错误 COMP96_0015：“';' 预期的。” “设计.vhd” 24 8
  2. COMP96 错误 COMP96_0019：“预期关键字‘结束’。” “设计.vhd” 24 8
  3. COMP96 错误 COMP96_0016：“需要设计单元声明。” “设计.vhd”24 11

我怎么能这样做？

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1 回答 1

0

正如user1155120所说，问题出在：

如果第 24 行的 l3 => 变成 l3 <= 会发生什么？这里不需要括号，条件由保留字限定。

我改变并工作。

于 2020-09-29T12:26:40.537 回答