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我目前正在设计一个由 MUXES 和全加器组成的 4 位 ALU。我即将完成，但在我的测试台上遇到了一些错误。我真的很感激这方面的任何帮助！如您所知，此错误表明我仍然是 VHDL 的初学者。

错误：Enumeration literal 'Z' is not of type ieee.std_logic_1164.std_logic_vector

Z 是 0 或 1，我在其中声明输入值。

我原来的模块代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY lab2 IS
    PORT(A, B: IN bit_vector(3 downto 0);
            Cin,S1,S0: IN bit;
            Cout: OUT bit;
            F: OUT bit_vector(3 downto 0));
    End lab2;

ARCHITECTURE Structure of lab2  IS

    COMPONENT MUX_A IS
    PORT(A, S0, S1: IN bit;
            X: OUT bit);
    END COMPONENT;

    COMPONENT MUX_B IS
    PORT(B, S0, S1: IN bit;
            Y: OUT bit);
    END COMPONENT;

    COMPONENT Full_Adder
            PORT (A_IN,B_IN,Cin: IN bit;
            Cout, F: OUT bit);
    END COMPONENT;

SIGNAL A_OUT: bit_vector (3 downto 0); 
SIGNAL B_OUT: bit_vector (3 downto 0);
SIGNAL Cout1, Cout2, Cout3: bit; 

BEGIN

    MUXA0: MUX_A PORT MAP(A(0), S0, S1, A_OUT(0));
    MUXA1: MUX_A PORT MAP(A(1), S0, S1, A_OUT(1));
    MUXA2: MUX_A PORT MAP(A(2), S0, S1, A_OUT(2));
    MUXA3: MUX_A PORT MAP(A(3), S0, S1, A_OUT(3));

    MUXB0: MUX_B PORT MAP(B(0), S0, S1, B_OUT(0));
    MUXB1: MUX_B PORT MAP(B(1), S0, S1, B_OUT(1));
    MUXB2: MUX_B PORT MAP(B(2), S0, S1, B_OUT(2));
    MUXB3: MUX_B PORT MAP(B(3), S0, S1, B_OUT(3));

    Adder1_0: Full_Adder PORT MAP(A_OUT(0), B_OUT(0), Cin, Cout1, F(0));
    Adder1_1: Full_Adder PORT MAP(A_OUT(1), B_OUT(1), Cout1, Cout2, F(1));
    Adder1_2: Full_Adder PORT MAP(A_OUT(2), B_OUT(2), Cout2, Cout3, F(2));
    Adder1_3: Full_Adder PORT MAP(A_OUT(3), B_OUT(3), Cout3, Cout, F(3));


END Structure;

到目前为止我的测试台代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS
COMPONENT Lab2
    PORT(A, B: IN bit_vector(3 downto 0);
            Cin,S1,S0: IN bit;
            Cout: OUT bit;
            F: OUT bit_vector(3 downto 0));
END COMPONENT;

    --Declare inputs and initialize them
    SIGNAL A:bit_vector(3 downto 0);
    SIGNAL B:bit_vector(3 downto 0);
    SIGNAL Cin:bit;
    SIGNAL S1:bit;
    SIGNAL S0:bit;

    --Declare outputs and initialize them 
    SIGNAL Cout:bit;
    SIGNAL F:bit_vector(3 downto 0);

BEGIN
UUT: Lab2 PORT MAP (
    A => A,
    B => B,
    Cin => Cin,
    S1 => S1,
    S0 => S0,
    Cout => Cout,
    F => F);

    stim_proc: process
BEGIN
    --Declare input values of A & B
    A <= '0';
    B <= '0';
    wait for 20 ns;
    A <= '0';
    B <= '1';
    wait for 20 ns;
    A <= '1';
    B <= '0';
    wait for 20 ns;
    A <= '1';
    B <= '1';
    wait for 20 ns;

    --Declare input values for Cin
    Cin <= '0';
    wait for 20 ns;
    Cin <= '1';
    wait for 20 ns;

    --Declare Input values for S1 & S0
    S1 <= '0';
    S0 <= '0';
    wait for 20 ns;
    S1 <= '0';
    S0 <= '1';
    wait for 20 ns;
    S1 <= '1';
    S0 <= '0';
    wait for 20 ns;
    S1 <= '1';
    S0 <= '1';
    wait for 20 ns;

END process;

END;
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