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我是 fpga 和 vhdl 新手..

我的开发环境如下。

FPGA：斯巴达6 XC6SLX9

编译器：ISE 14.04

模拟器：Isim

我正在做一个简单的计数器，但有些东西我无法理解。

下面的代码是我写的。我期望的是w_count在时钟的每个下降沿增加，并在时钟上升沿w_count达到时重置为 0。N_data编译过程没有问题，仿真也和我预期的一样好。但是当应用于真正的 fpga 时，w_count每个触发器都会递增，但在达到N_data..时不会初始化为零。

w_state_proc : process(r_clk, reset_n_clean)
begin
    if(reset_n_clean = '0') then
        w_count <= 0;
    elsif(r_clk'event and r_clk = '0') then
        if(state = write_state and w_proc = '1') then
            w_count <= w_count + 1;
        end if;
    elsif(r_clk'event and r_clk = '1') then
        if(w_count = N_data) then
            w_count <= 0;
        end if;
    end if;
end process w_state_proc;

当我改变两个elsif语句的位置时，w_count根本没有增加..

w_state_proc : process(r_clk, reset_n_clean)
begin
    if(reset_n_clean = '0') then
        w_count <= 0;
    elsif(r_clk'event and r_clk = '1') then
        if(w_count = N_data) then
            w_count <= 0;
        end if;
    elsif(r_clk'event and r_clk = '0') then
        if(state = write_state and w_proc = '1') then
            w_count <= w_count + 1;
        end if;
    end if;
end process w_state_proc;

我可以看到很多不推荐这些语句的反馈，但我不明白为什么这些语句会导致这个问题..

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1 回答 1

4

您的 FPGA 在通用结构中没有双数据速率 (DDR) 触发器，这就是不建议使用它的原因 - “按原样”它无法实现所需的功能。

此外，您正在使用异步重置。虽然可能，但也强烈不推荐，因为 FPGA 已经具有同步复位触发器，因此它不需要任何额外的逻辑，这与 ASIC 不同，即使没有复位，您也可以获得每个信号的已知值。异步复位会给您以一种或另一种方式实现时序收敛带来麻烦。

In your example, there is really no need for DDR FFs anyhow. It would seem that the reason to have the behavior you have is that the w_count can be cleared between the clock cycles so that w_count never is N_data when incremented. Why not have the compare it to value that is one smaller?

Or, you could use variables (very carefully!) to achieve very similar behavior:

  w_state_proc : process(r_clk) is
    variable v_count : integer range 0 to N_data;
  begin
    if (rising_edge(r_clk)) then
      v_count := w_count;
      if(state = write_state and w_proc = '1') then
        v_count := v_count + 1;
      end if;

      if(reset_n_clean = '0' or v_count = N_data) then
        w_count <= 0;
      else
        w_count <= v_count;
      end if;

    end if;
  end process w_state_proc;

If you would really need the w_count to have the value of N_data for half a clock cycle, you can always make the clock twice as fast and use enable signal active every other clock cycle, and propagate that alongside your pipeline. That'll get you in a whole host of other (very educational) trouble, but doable.

于 2017-04-19T09:47:44.933 回答