vhdl - State to std_logic

Question

I have defined my state as follows:

type state_type is (s0, s1, s2, s3);
signal state   : state_type;

Now I would like to use this state information to form another signal

signal data : std_logic_vector(3 downto 0);
signal data_plus_state : std_logic_vector(5 downto 0);

....
data_plus_state <= data & state;

Does anyone know how I can concert state into a std_logic_vector so that I can concatenate these two signals?

Many thanks, Rob

Answer 1

子程序和案例答案会很好地工作。如果你想要一些东西，你可以使用它。

signal state_slv : std_logic_vector(1 downto 0);

state_slv <= "00" when state = s0 else
             "01" when state = s1 else
             "10" when state = s2 else
             "11";

data_plus_state <= data & state_slv;

干杯

Answer 2

Define a subprogram that convert state to std_logic_vector.

That subprogram contains a case statement, something like:

case state is
  when s0 => return <std_logic_vector value for s0>;
  when s1 => return <std_logic_vector value for s1>;
  when s2 => return <std_logic_vector value for s2>;
  when s3 => return <std_logic_vector value for s3>;
end case;

Answer 3

您似乎想将两个（或更多）信号放入一个信号（或端口）中。

去这里的方法不是连接信号，而是将它们放入记录中。优点是信号各部分的语义（意义）表达清楚。这样您就不必编码（然后解码）每个数据元素。

type state_type is (s0, s1, s2, s3);
signal state   : state_type;
signal data : std_logic_vector(3 downto 0);
type data_plus_state_type is record
    data : std_logic_vector(3 downto 0);
    state: state_type;
end record data_plus_state_type;
signal data_plus_state : data_plus_state_type;

然后你可以把这两个信号放在一个记录信号中：

data_plus_state <= (data, state);
-- or:
data_plus_state.data <= data;
data_plus_state.state <= state;