verilog - 减去两个 32 位输入时出现 Icarus Verilog 语法错误？

Question

我在学习 Verilog 的第一周遇到了非常令人沮丧的经历。

我正在尝试编译以下代码 - 来自 mipsalu.v

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

当我尝试使用 编译它iverilog -o test mipsalu.v时，iverilog 告诉我

mipsalu.v:13: syntax error
I give up.

当我删除有问题的行并再次编译时，没有错误-

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      //6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

任何见解将不胜感激。谢谢！

编辑：值得一提的是，我正在使用 MinGW/MSYS 在 Windows 8.1 上运行 Icarus Verilog 版本 10

Answer 1