1

我是 Verilog 的新手，我需要为何时a等于、小于和大于创建一个 8 位比较器b。这是我的代码（没有错误）：

module MagnitudeComparator8bit (input signed [7:0]a,
                                input signed [7:0]b,
                                output eq,
                                output lt,
                                output gt);
    assign eq = a == b;
    assign lt = a < b;
    assign gt = a > b;
endmodule

这就是我的测试平台，但是当我运行模拟时，我遇到了多个错误，但我不确定我哪里出错了。有什么帮助吗？

module MagnitudeComparatorTestbench;
    reg [7:0] a, b;
    wire eq, lt, gt;

    MagnitudeComparator8bit uut(
       .a(a),
       .b(b),
       .eq(eq),
       .lt(lt),
       .gt(gt)
    );

    initial begin
          $monitor (“%d %b %b %d %d %d”, $time, a, b, eq, lt, gt);
          a=8’b11110000;
          b=8’b11110000;
      #10 a=8’b1001001;
          b=8’b10101010;
      #10 a=8’b11001100;
          b=8’b10101000;
      #10 $finish
   end  
endmodule

错误：

testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: syntax error
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: unmatched character (hex ?)
testbench.sv:e: error: malformed statement
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: error: unmatched character (hex ?)
testbench.sv:f: syntax error
testbench.sv:f: error: malformed statement
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: error: unmatched character (hex ?)
testbench.sv:10: syntax error
testbench.sv:10: error: malformed statement
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: error: unmatched character (hex ?)
testbench.sv:11: syntax error
testbench.sv:11: error: malformed statement
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: error: unmatched character (hex ?)
testbench.sv:12: syntax error
testbench.sv:12: error: malformed statement
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: error: unmatched character (hex ?)
testbench.sv:13: syntax error
testbench.sv:13: error: malformed statement
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: error: unmatched character (hex ?)
testbench.sv:14: syntax error
testbench.sv:14: error: malformed statement
testbench.sv:16: syntax error
Exit code expected: 0, received: 40
4

2 回答 2

0

我尝试了您的代码，唯一的问题是 $finish 后缺少分号。所以 #10 $finish;

于 2016-01-29T00:35:25.390 回答
0

您的帖子中有奇怪的引号字符。在我复制并粘贴您的代码后，这些给了我错误。我修正了引号。复制此代码：

module MagnitudeComparatorTestbench;
    reg [7:0] a, b;
    wire eq, lt, gt;

    MagnitudeComparator8bit uut(
       .a(a),
       .b(b),
       .eq(eq),
       .lt(lt),
       .gt(gt)
    );

    initial begin
          $monitor ("%d %b %b %d %d %d", $time, a, b, eq, lt, gt);
          a=8'b11110000;
          b=8'b11110000;
      #10 a=8'b1001001;
          b=8'b10101010;
      #10 a=8'b11001100;
          b=8'b10101000;
      #10 $finish;
   end  
endmodule

我还在 $finish 之后添加了一个半成品。

于 2016-01-29T00:32:10.860 回答