我有以下双端口 RAM 内存的硬件描述:
module MemoryRAM #(parameter RAM_ADDR_BITS = 4, RAM_WIDTH = 8)
(CLK, RAMEnableLSB, RAMEnableMSB, WriteMemory,LoadData, Address, OutputRAMMEM);
input RAMEnableLSB, RAMEnableMSB ,WriteMemory;
input CLK;
reg [RAM_WIDTH-1:0] RAM1 [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] OutputData1 = 0,OutputData0 = 0;
input [RAM_ADDR_BITS-1:0] Address;
input [2*RAM_WIDTH-1:0] LoadData;
output [2*RAM_WIDTH -1:0] OutputRAMMEM;
always @ (posedge CLK)
begin
if(RAMEnableMSB) begin
if (WriteMemory)
begin
RAM1[Address+1] <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH]; // Bit MSB
OutputData1 <= LoadData[2*RAM_WIDTH-1:1*RAM_WIDTH];
end
else
begin
OutputData1 <= RAM1[Address+1]; // Bit MSB
end
end
else
OutputData1 <= 0;
end
always @ (posedge CLK)
begin
if(RAMEnableLSB) begin
if (WriteMemory)
begin
RAM1[Address] <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH]; // Bit LSB
OutputData0 <= LoadData[1*RAM_WIDTH-1:0*RAM_WIDTH];
end
else
begin
OutputData0 <= RAM1[Address]; // Bit LSB
end
end else
OutputData0 <= 0;
end
assign OutputRAMMEM = {OutputData1,OutputData0};
endmodule
当我在 Xilinx ISE 14.7 中进行综合时,一条消息告诉我综合是正确的。如果我还执行了行为模拟,则结果是预期的。
但是,如果我执行了 Post-Route 模拟,则会出现一条警告消息:
WARNING:HDLCompiler:1007 - "N:/O.61xd/rtf/verilog/src/unisims/ARAMB36_INTERNAL.v" Line 1050: Element index 7 into memp is out of bounds
并且模拟不起作用!!!!重要的一点是我正在使用 ISim 模拟器。如果我描述了单端口 RAM 的硬件,也会出现相同的警告。
谁能告诉我如何解决这个警告?