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我编写了以下代码，它产生不同宽度的脉冲。我希望代码根据选择线产生单个脉冲。如果选择线是

00 脉冲宽度 = 1 us，01 脉冲宽度 = 10 us。. 11 脉冲宽度 = 1000 us

输入时钟为 10 Mhz。但是根据代码，如果我不提供选择线的任何其他值，我会得到连续脉冲。我怎样才能只实现一个脉冲？

    module pulse(input wire [1:0] sel , //selection lines s1 s0
        input clk,
        input rst_n,
        output reg flag,    //for checking conditions
        output reg [13:0] Q,    // output of 14 bit counter
        output reg pulse,   //output pulse
        output reg count);  //also for checking conditions

wire flag_d , count_d;

assign flag_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : flag;
assign count_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : count;

always @(posedge clk , negedge rst_n)
begin
    if(!rst_n)
    begin
        Q <= 14'h0;
        count <= 1'b0;
        pulse <= 1'b0;
        flag <= 1'b0;
    end
    else
    begin

        flag <= flag_d;
        count <= count_d;

        if(flag)
        begin
            case(sel)
            2'b00: Q <= 14'd11;//count from 11 to 1
            2'b01: Q <= 14'd101;//count from 101 to 1
            2'b10: Q <= 14'd1001;//count from 1001 to 1
            2'b11: Q <= 14'd10001;//count from 10001 to 1
            default: Q <= 14'd0;    
            endcase

            flag <= 1'b0;
        end
        else
        begin
            if(Q != 14'h1 && Q != 14'h0)
            begin
                Q <= Q - 14'h1;
                pulse  <= 1'b1;
            end
            else
            begin
                pulse <= 1'b0;
                count <= 1'b0;
            end
        end  
    end
end 
endmodule

考虑到电路的综合和硬件，这段代码是否具有良好的编码风格？如果不是我应该应用哪些更改？...

4

2 回答 2

2

我无法弄清楚flag_dand的意义count_d。也( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)简化为(count == 1'b0). sel不应该是 Xs 或 Zs。

我认为您想要更多类似以下的内容：

reg [13:0] next_Q;
always @* begin
  if (Q==0) begin
    case(sel)
    2'b00 : next_Q = 14'd10;
    2'b01 : next_Q = 14'd100;
    2'b10 : next_Q = 14'd1000;
    2'b11 : next_Q = 14'd10000;
    endcase
  end
  else begin
    next_Q = Q - 1;
  end
end
always @(posedge clk, negedge rst_n) begin
  if (!rst_n) begin
    pulse <= 1'b0;
    Q <= 14'd0;
  end
  else begin
    // if (Q==0) pulse <= !pulse; // high and low pulse will have equal if sel is constant
    pulse <= (Q!=0); // or high pulse based on sel, low is one clk
    Q <= next_Q;
  end
end

工作示例：http ://www.edaplayground.com/x/GRv

于 2015-08-27T05:51:52.917 回答
1 
         module pulse(input wire [1:0] sel,         // No need for the sel to be wire 
        input   clk,
        input rst_n,
        output reg [13:0] Q,    
        output reg pulse,   
        input   input_stb,                  // Input is valid
        input   output_ack,     
        output  output_stb,         
        output  input_ack);                // 2 Flag model 

reg s_input_ack ;
reg s_output_stb;
 parameter get_inputs         = 4'd0,
        counter               = 4'd1;

always @(posedge clk , negedge rst_n)
begin

case (state)
    get_inputs:
    s_input_ack <= 1;
    if (s_input_ack && input_a_stb) 
    begin
    s_input_ack <= 0;
            case(sel)
            00: Q <= 14'd11;//00000000001010;
            01: Q <= 14'd101;//00000001100100;
            10: Q <= 14'd1001;//00001111101000;
            11: Q <= 14'd10001;//10011100010000;
            default: Q <= 14'd0;    
            endcase
    state <= counter;
    end

    counter:
        begin
        s_output_stb <= 1;
        if (s_output_stb && output_z_ack)
            begin
                        s_output_stb <= 0;

                if(Q != 14'h1 && Q != 14'h0)
                    begin
                    Q <= Q - 1'b1;
                    pulse  <= 1'b1;
                    end
                else
                    begin
                    pulse <= 1'b0;
                    end
                end
        state <= get_inputs;
        end 

endcase
        if(!rst_n)
    begin
        Q <= 14'h0;
        pulse <= 1'b0;
              s_input_ack <= 0;
              s_output_stb <= 0;
    end
      assign input_ack = s_input_ack;

分配 output_stb = s_output_stb; end endmodule *仍然需要工作，相应地添加寄存器和必要的信号。稍后会编辑

于 2015-08-26T07:26:12.313 回答