vhdl - 在 Xilinx 中测试 Assert 语句时出错

Question

我目前收到此错误

错误：HDLCompiler：1731 - 行 ...：找到运算符“=”的“0”定义，无法确定“=”的确切重载匹配定义

对于下面显示的最后 2 个断言语句（PulseOutput 和 IsCounting）。它不喜欢等号，但是您如何测试 1 位信号值？它上面的断言 (CountTemp) 没有收到错误。任何的想法？！

signal CountTemp : std_logic_vector(15 downto 0) := (others => '0');
signal PulseOutput  : std_logic;
signal IsCounting  : std_logic;
--------------------------------------------------------------
stim_proc:process
begin       
    SystemClear <= '1';
   -- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
   wait for 10 ns;
    assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
    assert (PulseOutput = 0) report "PulseOutput should equal 0 when System Clear is active" severity ERROR;    
    assert (IsCounting = 0) report "IsCounting should equal 0 when System Clear is active" severity ERROR;  
    wait for 10 ns;

Answer 1

std_logic位用撇号表示'，注意这在 VHDL中也称为记号。因此，例如在您的代码中：

stim_proc:process
begin       
    SystemClear <= '1';
   -- hold reset state for 10 ns, then test 3 signals, then hold for additional 10 ns
   wait for 10 ns;
    assert (CountTemp = X"0000") report "CountTemp should equal 0 when System Clear is active" severity ERROR;
    assert (PulseOutput = '0') report "PulseOutput should equal 0 when System Clear is active" severity ERROR;    
    assert (IsCounting = '0') report "IsCounting should equal 0 when System Clear is active" severity ERROR;  
    wait for 10 ns;