下面是我的一个简单（非时钟）4 位加法器的测试台代码。我的模拟当前将显示发生的任何错误以及最后的“测试完成”。如果没有错误，模拟将简单地返回“测试完成”。
我的问题是：
有没有办法以某种方式包含“if”语句，以便在模拟中未检测到错误时显示“测试完成，没有错误”，并在模拟中显示“测试完成，发现 [x] 错误”在模拟中检测到错误（其中 x 是模拟完成时返回的可变错误数量。）？
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder_4bit_TB IS
END adder_4bit_TB;
ARCHITECTURE behavior OF adder_4bit_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT adder_4bit
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
carry : OUT std_logic;
sum : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal carry : std_logic;
signal sum : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: adder_4bit PORT MAP (
a => a,
b => b,
carry => carry,
sum => sum
);
-- Stimulus process
stim_proc: process -- No CLK
begin
-- Initialize Input values
a <= "0000";
b <= "0000";
--Loop over all values of "a" and check sum
for I in 0 to 15 loop
--Loop over all values of "b" and check sum
for J in 0 to 15 loop
-- Wait for output to update (10 ns)
wait for 10ns;
-- Below is the self-verification routune being implemented for the 4 bit Adder.
-- The routine checks the sum of "a" and "b" at the end of every loop, and
-- reports any Errors that may have occured. If no errors occur, simulation
-- will return "Test Completed" (line109) in Command Window.
assert (sum = a + b) report "Expected sum of " &
integer'image(to_integer(unsigned((a + b)))) & ". For a = " &
integer'image(to_integer(unsigned((a)))) & " and b = " &
integer'image(to_integer(unsigned((b)))) & ", but returned sum was " &
integer'image(to_integer(unsigned((sum)))) severity ERROR; -- severity level can be NOTE, WARNING, ERROR, or FAILURE
-- Increment to next value of four bit vector "b"
b <= b + "0001";
end loop;
-- Increment to next value of four bit vector "a"
a <= a + "0001";
end loop;
--Echo to user that report has finished
report "Test completed";
wait; --will wait forever
end process;
END;
使用下面的答案，这是生成的工作代码：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder_4bit_TB IS
END adder_4bit_TB;
ARCHITECTURE behavior OF adder_4bit_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT adder_4bit
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
carry : OUT std_logic;
sum : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal carry : std_logic;
signal sum : std_logic_vector(3 downto 0);
--Outputs (Testbench only)
signal Errors : boolean; -- Boolean value. True if error detected. False if no error detected.
signal ErrorCount : integer := 0; -- Integer value to store the qty of errors. Intitialized to zero
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: adder_4bit PORT MAP (
a => a,
b => b,
carry => carry,
sum => sum
);
-- Stimulus process
stim_proc: process -- No CLK
begin
-- Initialize Input values
a <= "0000";
b <= "0000";
--Loop over all values of "a" and check sum
for I in 0 to 15 loop
--Loop over all values of "b" and check sum
for J in 0 to 15 loop
-- Wait for output to update (10 ns)
wait for 10ns;
-- Below is the self-verification routune being implemented for the 4 bit Adder.
-- The routine checks the sum of "a" and "b" at the end of every loop, and
-- reports any Errors that may have occured.
if (sum /= a + b) then ---- "/=" syntax: test for inequality, result is boolean
Errors <= true;
ErrorCount <= ErrorCount + 1;
else
Errors <= false;
end if;
assert (Errors = false) report "Expected sum of " &
integer'image(to_integer(unsigned((a + b)))) & ". For a = " &
integer'image(to_integer(unsigned((a)))) & " and b = " &
integer'image(to_integer(unsigned((b)))) & ", but returned sum was " &
integer'image(to_integer(unsigned((sum)))) severity ERROR; -- severity level can be NOTE, WARNING, ERROR, or FAILURE
-- Increment to next value of four bit vector "b"
b <= b + "0001";
end loop;
-- Increment to next value of four bit vector "a"
a <= a + "0001";
end loop;
--Echo to user that report has finished
report "Test completed with " & integer'image(ErrorCount) & " errors";
wait; --will wait forever
end process;
END;