我正在尝试构建一个脉冲发生器，它由两个由 mod-m 计数器驱动的脉冲发生器组成。计数器以设定的时间循环通过一个周期，每当它达到某个指定的时间时，脉冲发生器就会在这些时间产生短的方波脉冲。
这在模拟中有效，但是当我在我的 FPGA 板上实现它时，它将成功运行一个方波脉冲周期，但随后卡住，就好像计数器永久卡在 0（输出myag_q并byag_q卡在 0 和byag_l，myag_l卡在 1)。我已经自己模拟了计数器，并且知道它继续在 0 和 M 之间循环。
下面列出了顶层模块、mod-m 计数器和脉冲发生器的代码。另一个脉冲发生器与第一个非常相似。无需检查我的用户约束文件，因为我确信我得到了正确的引脚分配。我需要大致了解我在组合这些模块时是否犯了任何大错误/最后一个程序（脉冲发生器）是否正确编写。最重要的是，我需要知道我使用计数器触发脉冲的方式是否正确。
顶级模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity trigger is
Port ( clk, rst : in STD_LOGIC;
d: in STD_LOGIC_VECTOR(25 downto 0);
myag_l, myag_q, byag_l, byag_q : out STD_LOGIC);
end trigger;
architecture struc_arch of trigger is
signal counter: STD_LOGIC_VECTOR (25 downto 0);
begin
mini_yag: entity work.mini_yag(Behavioral)
port map(clk=>clk,rst=>rst,count=>counter,myag_l=>myag_l,myag_q=>myag_q);
big_yag: entity work.big_yag(Behavioral)
port map(clk=>clk,rst=>rst,d=>d,count=>counter,byag_l=>byag_l,byag_q=>byag_q);
baud: entity work.mod_m_counter(arch)
generic map(N=>26,M=>6434344)
port map(clk=>clk,reset=>rst,max_tick=>open,q=>counter);
end struc_arch;
Mod-M 计数器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mod_m_counter is
generic (
N: integer := 4; -- number of bits
M: integer := 10 -- mod-M
);
Port ( clk, reset : in STD_LOGIC;
max_tick : out STD_LOGIC;
q : out STD_LOGIC_VECTOR (N-1 downto 0));
end mod_m_counter;
architecture arch of mod_m_counter is
signal r_reg: unsigned (N-1 downto 0);
signal r_next: unsigned (N-1 downto 0);
begin
--register
process(clk,reset)
begin
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;
--next-state logic
r_next <= (others=>'0') when r_reg=(M-1) else
r_reg + 1;
--output logic
q <= std_logic_vector(r_reg);
max_tick <= '1' when r_reg=(M-1) else '0';
end arch;
脉冲发生器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity big_yag is
generic(
T1: unsigned :=to_unsigned(0,26); --Lamp On
T2: unsigned :=to_unsigned(138889,26); --Lamp Off
T3: unsigned :=to_unsigned(4305555,26); --Q-switch On
T4: unsigned :=to_unsigned(4343434,26); --Q-switch Off
T5: unsigned :=to_unsigned(6434343,26) --Reset Sequence
);
Port(
clk,rst : in STD_LOGIC;
d,count: in STD_LOGIC_VECTOR(25 downto 0);
byag_l,byag_q : out STD_LOGIC
);
end big_yag;
architecture Behavioral of big_yag is
signal delay,counter: unsigned (25 downto 0);
signal byag_l_reg,byag_l_next,byag_q_reg,byag_q_next: std_logic;
begin
delay <= unsigned(d);
counter <= unsigned(count);
--register
process(rst,clk)
begin
if rst='1' then
byag_l_reg <= '0';
byag_q_reg <= '0';
elsif (clk='1' and clk'event) then
byag_l_reg <= byag_l_next;
byag_q_reg <= byag_q_next;
end if;
end process;
--next state logic
byag_l_next <= '1' when counter = T1+delay else
'0' when counter = T2+delay else
byag_l_reg;
byag_q_next <= '0' when counter = T1+delay else
'1' when counter = T3+delay else
'0' when counter = T4+delay else
byag_q_reg;
--output logic
byag_l <= byag_l_reg;
byag_q <= byag_q_reg;
end Behavioral;