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我一直试图在 Nexys 3 (Spartan 6) 板上实现一个简单的序列检测器。该代码在 Xilinx 仿真上完美运行，但在硬件上却无法运行。由于我是 FPGA 实现的新手，我无法解决这个问题。我不知道应该对代码进行哪些更改才能在硬件中工作。如果有人可以帮助我，那就太好了..

这是代码

    module sequence( in, clock,reset,test);
    input in;
    input reset;
    output reg test=0;
    reg [3:0] state=0, next=0 ;
    input clock;



    always@( posedge clock)
    begin
    if(reset==1)
    begin
    state= 0;
    end
    else
    begin
    state=next;
    end
    end

    always @*
    begin

    if(reset == 1)
    begin
    next=0;
    test=0;  
    end
    else
    begin

    case ( state )

    'd0 : begin
      if ( in==1)
             begin
                next=state+1;
                end

         else
         next=next;
         end

    'd1 : begin
      if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
           end 

       'd2 : begin
          if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
          end

     'd3 : begin
           if ( in==1)
             begin
                next=state+1;
            end

         else
         next=0;
          end

         'd4 : begin
               if ( in==1)
                 begin
                 next=state+1;
                test=1;
            end

         else
         next=0;
          end

      default : begin

                next=0;
                test=0;
            end

       endcase
       end
       end
       endmodule
4

2 回答 2

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I would change the beginning of your always block to:

always @*
begin
  next = state;
  test = 0;

  case (state)
    'd0 :
      begin
        if ( in==1)
          next=state+1;
      end
  ...

Setting a default assignment to all values in the state machine eliminates the possibility of creating an implicit latch. Your "next = next" statement shouldn't have any effect but might be creating latch (should probably be "next = state').

Also test is not assigned in every branch and has no default, so it will also create a latch.

于 2015-03-26T17:24:47.060 回答
0

我在您的 Verilog 代码中发现的问题如下所示。

  • test必须在每个 case 语句分支中分配输出变量，否则会形成不需要的锁存器。

  • nonblocking assignments在指定时序电路时使用。

尝试如下编码您的序列检测器。

//sequence detector 101101

module fsm (rst,in1,clk,out1);

parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;

input rst,in1,clk;
output reg out1;

reg [2:0] state;

always @(posedge clk)
  if (rst)
    begin
      state <= s0;
      out1  <= 0 ;
    end
  else
      case(state)
              s0 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s1 : if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s2 : if (in1) begin state <= s3; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s3 : if (in1) begin state <= s4; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s4 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s5; out1 <= 0 ; end
              s5 : if (in1) begin state <= s1; out1 <= 1 ; end
                    else     begin state <= s0; out1 <= 0 ; end
        default: if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
      endcase

endmodule
于 2015-03-26T18:02:20.797 回答