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我正在研究 t-bird 灯控制器，我的代码中不断出现这些错误，当我浏览代码时，它并没有什么问题！我在VHDL方面没有太多经验，但我可以判断它是对还是错，请我需要你的帮助

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

 entity tbird is
 PORT(clk, lts,rts,haz,brake: IN bit;
 lc,lb,la,ra,rb,rc: OUT bit);
 end tbird;

 architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle => 
 IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  IF(brake='1') THEN next_state <= lr4;
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')next_state <=lr4;
  else next_state <= idle;
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;

这些是错误

 INFO:HDLCompiler:1061 - Parsing VHDL file "D:/ISE/DSD LABS/assigment/brake.vhd" into library work
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 53: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 55: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 56: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 58: Syntax error near "case".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 63: Syntax error near "BEGIN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 75: Syntax error near "PROCESS".
 ERROR:ProjectMgmt - 6 error(s) found while parsing design hierarchy.
4

3 回答 3

3

在行中：WHEN lr4=>IF(brake='1')next_state <=lr4;

这个词THEN不见了。

于 2014-12-15T15:12:38.787 回答
0

请注意您的错误消息行号与您的 VHDL 代码示例不匹配。

使您的 VHDL 示例无法分析的事情：

architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle =>  -- brake NOT break
 IF(haz='1' OR (lts='1' AND rts='1' AND brake='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  ELSIF(brake='1') THEN next_state <= lr4;  -- ELSIF was IF
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')THEN next_state <=lr4; -- MISSING THEN
  else next_state <= idle;
  END IF;                       -- MISSING ENDIF
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;

您在选择第二个流程的 case 语句时使用break了而不是。brakeidle

在选择r2相同的 case 语句时，您似乎打算使用第二IF个ELSIF。

在选择lr4相同的 case 语句时，您THEN在 if 语句中的赋值之前缺少 a。

您缺少ENDIF相同的 if 语句。

您还可以注意到您不需要上下文子句（实体声明之前的库和使用语句）。您的输入和输出端口都是 BIT 类型，唯一声明的其他信号是 type state_type。

这可能是您的代码看起来像美化的样子：

-- library ieee;                  -- NOT NEEDED
-- use ieee.std_logic_1164.all;   -- NOT NEEDED
-- use ieee.std_logic_arith.all;  -- NOT NEEDED

 entity tbird is
     port (
         clk, lts,rts,haz,brake:    in  bit;
         lc,lb,la,ra,rb,rc:         out bit
     );
 end tbird;

 architecture prettified of tbird is
     type state_type is (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
     signal state, next_state: state_type;
 begin
STATE_REG:
     process 
     begin
         wait until clk = '1' and clk'event;
         state <= next_state;
     end process;
NEXTSTATE:
    process(state,rts,lts,haz,brake)
    begin
        case state is
            when idle => 
                 if haz = '1' or (lts = '1' and rts = '1' and brake = '0') then -- brake NOT break
                     next_state <= lr3;
                 elsif haz = '0' and lts ='0' and brake ='0' and rts = '1' then 
                     next_state <= r1;
                 elsif haz = '0' and lts = '1' and brake = '0' and rts = '0' then 
                     next_state <= l1;
                 elsif haz = '0' and lts = '0' and brake = '1' and rts = '0' then 
                     next_state <= lr4;
                 else
                     next_state <= idle;
                 end if;
            when l1 => 
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= l2;
                end if;
            when l2 => 
                if haz='1' then 
                    next_state<= lr3;
                elsif brake ='1' then 
                    next_state <= lr4;
                else 
                    next_state <= l3;
                end if;
            when l3 =>
                next_state <=idle;
            when r1 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= r2;
                end if;
            when r2 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then  -- WAS if looks like should be elsif
                    next_state <= lr4;
                else 
                    next_state <= r3;
                end if;
            when r3 => 
                next_state <= idle;
            when lr3 => 
                next_state <= idle;
            when lr4 => 
                if brake = '1' then       -- MISSING then
                    next_state <= lr4;
                else 
                    next_state <= idle;
                end if;                 -- MISSING endif
        end case;
    end process;
MOORE_OUTPUTS:    
    process(state)
    begin
        case state is
            when idle =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '0'; rb <= '0'; rc <= '0';
            when l1 =>
                lc <= '0'; lb <= '0'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l2 =>
                lc <= '0'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when r1 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '0'; rc <= '0';
            when r2 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '0';
            when r3 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '1';
            when lr3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1'; 
            when lr4 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1';
        end case;
    end process;
end architecture;

使用标签的想法使您不必以迂回的方式指向事物，一致地使用空格和缩进使代码更易于阅读，并且我删除了不需要的括号对。

我很想MOORE_OUTPUTS使用索引的常量数组来不同地表达这个过程state_type'pos(state)。它会更紧凑，更容易修改。新声明可以是流程声明声明项（在 之前begin）。

该过程可能如下所示：

MOORE_OUTPUTS:
    process (state)
    type state_outputs is array (state_type'pos(idle) to state_type'pos(lr4)) 
        of bit_vector(0 to 5);
    constant outputs: state_outputs := ( 
                      -- lc   lb   la   ra   rb   rc
                        ('0', '0', '0', '0', '0', '0'), -- idle
                        ('0', '0', '1', '0', '0', '0'), -- l1
                        ('0', '1', '1', '0', '0', '0'), -- l2
                        ('1', '1', '1', '0', '0', '0'), -- l3
                        ('0', '0', '0', '1', '0', '0'), -- r1
                        ('0', '0', '0', '1', '1', '0'), -- r2
                        ('0', '0', '0', '1', '1', '1'), -- r3
                        ('1', '1', '1', '1', '1', '1'), -- lr3
                        ('1', '1', '1', '1', '1', '1')  -- lr4
                    ); 
    begin
        (lc, lb, la, ra, rb, rc) <= outputs(state_type'pos(state));
    end process;

它提供了一个可以直接操作的漂亮表格。

虽然我分析和阐述了这两种架构，但都没有被模拟过。

于 2014-12-15T19:00:23.840 回答
0

在以下代码中，将“break”重命名为“brake”。您在实体中声明了“刹车”：

IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;

在下面的代码end if;中，在行尾添加语句：

WHEN r2=>IF(haz='1') THEN next_state <= lr3;

在下面的代码中，在正确的地方使用then和end if;语句：

WHEN lr4=>IF(brake='1')next_state <=lr4;
    else next_state <= idle;
END case;

通过上述更改，语法错误将被删除。

于 2014-12-15T16:35:16.993 回答