我正在做一个项目，但无法连接顶部模块中的组件。我只是看不出我做错了什么。任何建议都受到高度赞赏。
除了看不到 RTL 原理图中的组件外，我还收到了一些警告：
WARNING:Xst:1290 - Hierarchical block <u0> is unconnected in block <TOP>.
It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <u1> is unconnected in block <TOP>.
It will be removed from the design.
WARNING:Xst:2677 - Node <u1/calc_deb> of sequential type is unconnected in block <TOP>.
WARNING:Xst:2677 - Node <u1/flipflops_1> of sequential type is unconnected in block <TOP>.
WARNING:Xst:2677 - Node <u1/flipflops_0> of sequential type is unconnected in block <TOP>.
所以这里是顶层模块的实现：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TOP is
port(
calc: in std_logic;
OP: in std_logic_vector(1 downto 0);
inValue: in std_logic_vector(3 downto 0);
clk: in std_logic
);
end TOP;
architecture Behavioral of TOP is
component alu port(
OP : in std_logic_vector(1 downto 0);
inValue : in std_logic_vector(3 downto 0);
regValue : in std_logic_vector(3 downto 0);
result: out std_logic_vector(4 downto 0);
clk : in STD_LOGIC
);
end component;
component debouncer port(
calc : in STD_LOGIC;
calc_deb : out STD_LOGIC;
clk: in std_logic
);
end component;
signal calc_debaux: std_logic;
signal regValueaux: std_logic_vector(3 downto 0);
signal resultaux: std_logic_vector(4 downto 0);
--signal OP: std_logic_vector(1 downto 0);
--signal OP: std_logic_vector(3 downto 0);
begin
u0: alu port map(OP => OP, inValue=>inValue, regValue=>regValueaux, result=>resultaux, clk=>clk);
u1: debouncer PORT MAP(calc=>calc, alc_deb=>calc_debaux, clk=>clk);
end Behavioral;
这是我在顶部模块中实例化的两个实体：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( OP : in std_logic_vector(1 downto 0);
inValue : in std_logic_vector(3 downto 0);
regValue : in std_logic_vector(3 downto 0);
result: out std_logic_vector(4 downto 0);
clk : in STD_LOGIC
);
end ALU;
architecture archi of alu is
signal res_temp: std_logic_vector(4 downto 0);
signal aux1, aux2: std_logic_vector(4 downto 0);
begin
aux1 <= ('0' & inValue);
aux2 <= ('0' & regValue);
result <= res_temp;
process (inValue, OP)
begin
case OP is
when "00" =>
res_temp <= (aux1) + (aux2) ;
when "01" =>
res_temp <= aux1 - aux2;
when "10" =>
res_temp <= (inValue and regValue);
when others =>
res_temp <= '0' & (regValue(0) & regValue(3 downto 1));
end case;
end process;
end archi ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debouncer is
Port ( calc : in STD_LOGIC;
calc_deb : out STD_LOGIC;
clk: in std_logic);
end debouncer;
architecture Behavioral of debouncer is
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= calc;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(8) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
calc_deb <= flipflops(1);
END IF;
END IF;
END PROCESS;
end Behavioral;
我还收到更多警告：
Synthesizing Unit <TOP>.
Related source file is "D:/Mestrado/1o ano/1o semestre/PSD/Projectos/andgates/TOP.vhd".
WARNING:Xst:646 - Signal <resultaux> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <regValueaux> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:646 - Signal <calc_debaux> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <TOP> synthesized.
我在这方面花了很多时间（这是一个更大项目的一部分，我只是想通过逐步进行故障排除来重新启动），现在我一无所知。:(
感谢您的时间。