I am trying to analyze the following file which is supposed to be VHDL-2008 compatible.
entity closely_related is
end;
architecture example of closely_related is
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
begin
process
variable int_vect: integer_vector(1 to 3);
variable real_vect: real_vector(1 to 3);
begin
real_vect := ( 1.0, 2.0, 3.0 );
int_vect := integer_vector( real_vect );
wait;
end process;
end;
This is supposed to be an experiment about closely related types. According to the LRM, there are two cases of closely related types:
— Abstract numeric types—Any abstract numeric type is closely related to any other abstract numeric type. — Array types—Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related
I understand that reals and integers are closely related; type conversion (aka type casting) between them works ok. Then why doesn't it work for the above array types?
GHDL gives the following error:
conversion not allowed between not closely related types
And Modelsim Altera 10.1e (with -2008 switch) is no better:
Illegal type conversion from std.STANDARD.REAL_VECTOR to std.STANDARD.INTEGER_VECTOR
(array element type difference).
Just to be thorough, I tried to do the same operation one element at a time:
int_vect(1) := integer( real_vect(1) );
int_vect(2) := integer( real_vect(2) );
int_vect(3) := integer( real_vect(3) );
And it works perfectly. Any ideas?