11

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL?

Example1:

always_comb begin
    gated_clk  = clk & latch_update_en;
end

always_latch begin
    if(gated_clk) begin
         latch_data <= new_data;
    end
end

Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this:

clock_gator cg_cell (.clk(clk), .en(latch_update_en), .scan_en(scan_en_in), .gated_clk(gated_clk));

always_latch begin
    if(gated_clk) begin
         latch_data <= new_data;
    end
end

What is the purpose of using custom clock gating cell? Does the tool have hard time in synthesis if clk is directly "and"-ed in a always_comb block with another enable signal? I am having a feeling that using special clock gating cell is a standard approach to generated gated clock signal. I am trying to understand why this is the case.

4

2 回答 2

14

在 RTL 中实现时钟门控的正确方法是什么？

时钟门控信号应仅在锁存器关闭时切换，否则可能会出现毛刺和亚稳态问题。对于高电平有效锁存器，门控信号应在时钟的下降沿触发。低电平有效锁存器的上升沿。

通常，您会使用边沿敏感触发器来保持latch_update_en以防止选通信号上的噪声。

always_ff @(negedge clk)
  latch_update_en <= next_latch_update_en;

always_comb
    gated_clk = (* clock_gating = "clk" *) clk & latch_update_en;

always_latch
    if(gated_clk)
         latch_data <= new_data;

提醒：如果您只有锁存器设计：边沿触发触发器只是主/从锁存器

always_latch 
    if (clk)
      sync_latch_update_en <= next_latch_update_en;
always_latch 
    if (!clk)
      latch_update_en <= sync_latch_update_en;

如果 clk 在带有另一个使能信号的 always_comb 块中直接“与”-ed，那么该工具是否很难进行综合？

大多数综合确实存在直接与时钟进行与运算的问题。如何使用门控并不总是直观的。合成器通常在库中有许多 AND 门可供选择，每个门都有不同的 slew、skew 和在输入组合上的加载。虽然功能相同，但A & B会得到不同的时间结果B & A。

从合成器的库中实例化一个显式单元缩小了了解和预期行为的可能性。预定义的时钟门控单元还具有合成器使用的属性。属性包括用于平衡时钟树的时序信息（设计中用于管理负载和寄生的缓冲区布局）。

一些合成器支持在 RTL 中设置属性标签（例如：// synthesis attributes或(* attributes *)），而不需要显式实例化一个单元格。没有关于如何做到这一点的标准，请参阅您的用户手册。

使用自定义时钟门控单元的目的是什么？

自定义单元是综合库中的一个自定义单元，具有已知的时序信息、负载平衡和其他属性。有了这些信息，合成器就知道在哪里以及如何在时钟树中添加或校准缓冲器延迟。这确保了非门控触发器在门控触发器之前看不到时钟边沿。

                 _____       _____
IN -------------|D   Q|-----|D   Q|--- OUT
                |     |     |     |
       |\ |\    |     |     |     |
     +-| >| >---|>    |   +-|>    |
     | |/ |/    |_____|   | |_____|
     |  ___               |
CLK -+-|   \              |
       | &  )-------------+   BALANCED CLOCK : correct data sampled
GATE --|___/

没有指导，门控翻牌可能会延迟时钟。偏斜会导致错误的数据被采样。

                 _____       _____
IN -------------|D   Q|-----|D   Q|--- OUT
                |     |     |     |
                |     |     |     |
     +----------|>    |   +-|>    |
     |          |_____|   | |_____|
     |  ___               |
CLK -+-|   \    |\ |\     |
       | &  )---| >| >----+   UNBALANCED CLOCK : wrong data sampled
GATE --|___/    |/ |/
于 2014-07-28T20:41:51.450 回答
0

阅读Yu-Yun Dai 的论文：时钟门控电路的验证和综合，其中说：

需要对时钟门控电路进行顺序等效检查 (SEC)

此外，尝试https://github.com/YosysHQ/yosys-bigsim/blob/master/openmsp430/rtl/omsp_clock_gate.v，其中代码粘贴如下：

//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
//     * Redistributions in binary form must reproduce the above copyright
//       notice, this list of conditions and the following disclaimer in the
//       documentation and/or other materials provided with the distribution.
//     * Neither the name of the authors nor the names of its contributors
//       may be used to endorse or promote products derived from this software
//       without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_gate.v
// 
// *Module Description:
//                       Generic clock gate cell for the openMSP430
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------

module  omsp_clock_gate (

// OUTPUTs
    gclk,                      // Gated clock

// INPUTs
    clk,                       // Clock
    enable,                    // Clock enable
    scan_enable                // Scan enable (active during scan shifting)
);

// OUTPUTs
//=========
output         gclk;           // Gated clock

// INPUTs
//=========
input          clk;            // Clock
input          enable;         // Clock enable
input          scan_enable;    // Scan enable (active during scan shifting)


//=============================================================================
// CLOCK GATE: LATCH + AND
//=============================================================================

// Enable clock gate during scan shift
// (the gate itself is checked with the scan capture cycle)
wire    enable_in =   (enable | scan_enable);

// LATCH the enable signal
reg     enable_latch;
always @(clk or enable_in)
  if (~clk)
    enable_latch <= enable_in;

// AND gate
assign  gclk      =  (clk & enable_latch);


endmodule // omsp_clock_gate
于 2019-01-14T13:47:04.597 回答