我目前正在一个项目中工作，我必须采用斐波那契算法高级描述（C）并将其转换为用 VHDL 编写的 RTL 模块。为此，需要将这种高级描述转换为可合成的 VHDL 代码，即，必须以 IC 原型设计中广为人知的方法为数据路径和有限状态机 (FSM) 编写 VHDL 代码。
我在两个单独的文件中描述了数据路径和 FSM，并在第三个文件中将它们实例化为 VHDL 组件，定义了斐波那契模块。使用 Quartus II 软件，“Analysis & Synthesis”成功，没有错误，并带有非常恼人的警告“Warning (13024): Output pins is cast at VCC or GND”。使这个警告真正令人讨厌的是它显示了斐波那契模块的最关键输出，这是它的最终结果。此输出在我的代码中称为“d_o”。
“data_o”输出引脚来自数据路径组件，也使用加法器、减法器、寄存器和多路复用器等组件进行描述。单独编译（分析和综合）数据路径，对于相同的输出再次显示警告。
我真的不知道我的代码有什么问题，希望你们能帮助我。代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY datapath IS
GENERIC (NUMBITS : NATURAL := 32);
PORT ( SIGNAL rst : IN STD_LOGIC;
SIGNAL clk : IN STD_LOGIC;
---Sinal de entrada---
SIGNAL data_in : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
---Sinais de seleção---
SIGNAL di_sel : IN STD_LOGIC;
SIGNAL nf_sel : IN STD_LOGIC;
SIGNAL na1_sel : IN STD_LOGIC;
SIGNAL na2_sel : IN STD_LOGIC;
SIGNAL io_sel : IN STD_LOGIC;
SIGNAL so0_sel : IN STD_LOGIC;
SIGNAL so1_sel : IN STD_LOGIC;
---Sinais load---
SIGNAL nf_ld : IN STD_LOGIC;
SIGNAL di_ld : IN STD_LOGIC;
SIGNAL na1_ld : IN STD_LOGIC;
SIGNAL na2_ld : IN STD_LOGIC;
SIGNAL do_ld : IN STD_LOGIC;
---Sinais das comparações---
SIGNAL di_eq_0 : OUT STD_LOGIC;
SIGNAL di_eq_1 : OUT STD_LOGIC;
---Sinais de saída---
SIGNAL irq_o : OUT STD_LOGIC;
SIGNAL status_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL d_o : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END datapath;
ARCHITECTURE behavior OF datapath IS
---Componentes do datapath---
COMPONENT somador
GENERIC (NUMBITS : NATURAL := 32);
PORT ( SIGNAL x : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL y : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL XY : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;
COMPONENT subtrator
GENERIC (NUMBITS : NATURAL := 32);
PORT ( SIGNAL x : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL y : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL XY : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;
COMPONENT reg
GENERIC (NUMBITS : NATURAL := 32);
PORT( SIGNAL rst : IN STD_LOGIC;
SIGNAL clk : IN STD_LOGIC;
SIGNAL load : IN STD_LOGIC;
SIGNAL d : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL q : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;
COMPONENT multiplexor2a1
GENERIC (NUMBITS : NATURAL := 32);
PORT ( SIGNAL a : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL b : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL sel : IN STD_LOGIC;
SIGNAL f : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;
COMPONENT igual
GENERIC (NUMBITS : NATURAL := 32);
PORT ( SIGNAL a : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL b : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL eq : OUT STD_LOGIC);
END COMPONENT;
---Sinais de conexão---
SIGNAL mux2di : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2nf : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2na1 : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2na2 : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
---Saidas dos registradores---
SIGNAL nf_o : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL di_o : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL na1_o : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL na2_o : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
---Saidas do somador e do subtrator---
SIGNAL a_result : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL s_result : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
---Constatntes---
SIGNAL one : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL zero : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
BEGIN
zero <= "00000000000000000000000000000000";
one <= "00000000000000000000000000000001";
---Lógica para irq_o---
WITH io_sel SELECT
irq_o <= '0' WHEN '0', '1' WHEN OTHERS;
---Lógica para status_o---
WITH so0_sel SELECT
status_o(0) <= '0' WHEN '0', '1' WHEN OTHERS;
WITH so1_sel SELECT
status_o(1) <= '0' WHEN '0', '1' WHEN OTHERS;
---Multiplexadores(4)---
mux1: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (data_in, s_result, di_sel, mux2di);
mux2: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (one, nf_o, nf_sel, mux2nf);
mux3: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (zero, na1_o, na1_sel, mux2na1);
mux4: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (a_result, di_o, na2_sel, mux2na2);
---Registradores(5)---
d_i: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, di_ld, mux2di, di_o);
na1: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, na1_ld, mux2na1, na1_o);
na2: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, na2_ld, mux2na2, na2_o);
nf: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, nf_ld, mux2nf, nf_o);
do: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, do_ld, nf_o, d_o);
---Somador---
a: somador GENERIC MAP(NUMBITS) PORT MAP (na1_o, na2_o, a_result);
---Subtrator---
s: subtrator GENERIC MAP(NUMBITS) PORT MAP (di_o, one, s_result);
---Comparadores (2)---
eq0: igual GENERIC MAP(NUMBITS) PORT MAP (di_o, zero, di_eq_0);
eq1: igual GENERIC MAP(NUMBITS) PORT MAP (di_o, one, di_eq_1);
END ARCHITECTURE;
和警告：
"Warning (13024): Output pins are stuck at VCC or GND"
