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我在莱迪思半导体制造的 MachXO2 分线板上评估 FPGA。现在我正在尝试由 IPExpress 生成的 FIFO_DC 模块的 RTL 模拟。

我为 FIFO 模块创建了一个简单的测试平台。当我从仿真向导启动 Active-HDL 时，我收到以下错误消息。

我无法从 Lattice 获得任何支持，因为这项工作只是我的爱好，而不是我的工作。你能给我一个关于这个问题的建议吗？任何帮助，将不胜感激。提前致谢。

Active-HDL 控制台上的错误消息

ELAB2：致命错误：ELAB2_0036 未解析从模块“FifoTest_tb.fifo.FifoMacro_0_3”中对“PUR_INST.PURNET”的分层引用（未找到模块）。

示例 HDL

[FifoTest_tb.v] --> FIFO 模块的测试平台

`timescale 1ns/1ps

module FifoTest_tb();

parameter CLOCK_PERIOD = 10;
parameter LOOP_CYCLE = 100;
integer i;

reg [7:0] tb_data;
reg tb_ck;
reg tb_wen;
reg tb_ren;
reg tb_clr;
wire [7:0] tb_q;
wire tb_emp;
wire tb_full;
wire tb_aef;
wire tb_aff;


//module instantiation
FifoMacro fifo(
    .Data(tb_data),
    .WrClock(tb_ck),
    .RdClock(tb_ck),
    .WrEn(tb_wen),
    .RdEn(tb_ren),
    .Reset(tb_clr),
    .RPReset(tb_clr),
    .Q(tb_q),
    .Empty(tb_emp),
    .Full(tb_full),
    .AlmostEmpty(tb_aef),
    .AlmostFull(tb_aff)
    );

//Behavior 

always #(CLOCK_PERIOD/2) tb_ck = ~tb_ck;

initial begin
    tb_data = 0;
    tb_ck   = 0;
    tb_wen  = 0;
    tb_ren  = 0;
    tb_clr  = 1;

    @(negedge tb_ck) begin
        tb_clr <= 0;
        tb_wen <= 1;
    end 

    //Write cycle
    for(i=0; i<LOOP_CYCLE; i=i+1)begin
        @(negedge tb_ck) begin
            tb_data <= i % 256;
        end
    end


    //Write cycle
    @(negedge tb_ck) begin
        tb_wen <= 0;
        tb_ren <= 1;
    end

    for(i=0; i<LOOP_CYCLE; i=i+1)begin
        @(negedge tb_ck) begin
            tb_data <= i % 256;
        end
    end
    $stop;
    $finish;

end


endmodule





/* Verilog netlist generated by SCUBA Diamond_3.0_Production (94) */
/* Module Version: 5.5 */
/* C:\lscc\diamond\3.0\ispfpga\bin\nt\scuba.exe -w -n FifoMacro -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 4096 -width 8 -rwidth 8 -regout -resetmode ASYNC -reset_rel ASYNC -no_enable -pe 256 -pf 3840 -e  */
/* Tue Feb 25 21:38:17 2014 */

[FifoMacro.v] --> IPExpress自动生成的文件（FIFO_DC模块）

`timescale 1 ns / 1 ps
module FifoMacro (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
    Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [7:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [7:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire Empty_int;
    wire Full_int;
    wire scuba_vhi;
    wire scuba_vlo;

    defparam FifoMacro_0_3.FULLPOINTER1 = "0b01111111111110" ;
    defparam FifoMacro_0_3.FULLPOINTER = "0b10000000000000" ;
    defparam FifoMacro_0_3.AFPOINTER1 = "0b01110111111110" ;
    defparam FifoMacro_0_3.AFPOINTER = "0b01111000000000" ;
    defparam FifoMacro_0_3.AEPOINTER1 = "0b00001000000010" ;
    defparam FifoMacro_0_3.AEPOINTER = "0b00001000000000" ;
    defparam FifoMacro_0_3.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_0_3.GSR = "DISABLED" ;
    defparam FifoMacro_0_3.RESETMODE = "ASYNC" ;
    defparam FifoMacro_0_3.REGMODE = "OUTREG" ;
    defparam FifoMacro_0_3.CSDECODE_R = "0b11" ;
    defparam FifoMacro_0_3.CSDECODE_W = "0b11" ;
    defparam FifoMacro_0_3.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_0_3.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_0_3 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[0]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[1]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[0]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[0]), 
        .DO1(Q[1]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));

    defparam FifoMacro_1_2.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_1_2.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_1_2.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_1_2.GSR = "DISABLED" ;
    defparam FifoMacro_1_2.RESETMODE = "ASYNC" ;
    defparam FifoMacro_1_2.REGMODE = "OUTREG" ;
    defparam FifoMacro_1_2.CSDECODE_R = "0b11" ;
    defparam FifoMacro_1_2.CSDECODE_W = "0b11" ;
    defparam FifoMacro_1_2.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_1_2.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_1_2 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[2]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[3]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[2]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[2]), 
        .DO1(Q[3]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    defparam FifoMacro_2_1.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_2_1.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_2_1.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_2_1.GSR = "DISABLED" ;
    defparam FifoMacro_2_1.RESETMODE = "ASYNC" ;
    defparam FifoMacro_2_1.REGMODE = "OUTREG" ;
    defparam FifoMacro_2_1.CSDECODE_R = "0b11" ;
    defparam FifoMacro_2_1.CSDECODE_W = "0b11" ;
    defparam FifoMacro_2_1.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_2_1.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_2_1 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[4]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[5]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[4]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[4]), 
        .DO1(Q[5]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam FifoMacro_3_0.FULLPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.FULLPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.AFPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.AFPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.AEPOINTER1 = "0b00000000000000" ;
    defparam FifoMacro_3_0.AEPOINTER = "0b11111111111110" ;
    defparam FifoMacro_3_0.ASYNC_RESET_RELEASE = "ASYNC" ;
    defparam FifoMacro_3_0.GSR = "DISABLED" ;
    defparam FifoMacro_3_0.RESETMODE = "ASYNC" ;
    defparam FifoMacro_3_0.REGMODE = "OUTREG" ;
    defparam FifoMacro_3_0.CSDECODE_R = "0b11" ;
    defparam FifoMacro_3_0.CSDECODE_W = "0b11" ;
    defparam FifoMacro_3_0.DATA_WIDTH_R = 2 ;
    defparam FifoMacro_3_0.DATA_WIDTH_W = 2 ;
    FIFO8KB FifoMacro_3_0 (.DI0(scuba_vlo), .DI1(scuba_vlo), .DI2(Data[6]), 
        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(Data[7]), .DI6(scuba_vlo), 
        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
        .DI11(Data[6]), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), 
        .CSW1(scuba_vhi), .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), 
        .EMPTYI(Empty_int), .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), 
        .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[6]), 
        .DO1(Q[7]), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), 
        .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), 
        .DO17(), .EF(), .AEF(), .AFF(), .FF());

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule

开发环境

格子钻石 3.0.0.97

Active-HDL 版本 9.2

目标设备：LCMXO2-1200ZE-1TG144C

4

1 回答 1

2

将这些行添加到您的顶级测试台：

GSR GSR_INST (.GSR (<global reset sig>));
PUR PUR_INST (.PUR (<powerup reset sig>));

请参阅此 Lattice FPGA How To 文档： 如何使用全局设置/重置 (GSR) 信号

于 2014-03-20T05:57:29.857 回答