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您好我正在使用以下代码来设计一个 n 位计数器。根据开始和结束我想实例化向上或向下计数器。

但我收到“格式错误的声明”。请帮忙。

module nbitUpCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;

    output reg [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;

    // Increment count on clock
    always @(actlow or posedge clk or negedge rst_n)
    begin
       if (actlow == 0)
       begin
           if (rst_n==0) 
          count = startc;
       else if (count==endc) count=startc;
           else count = count + 1;
       end
    end
endmodule

module nbitDownCounter(startc,endc , clk, rst_n,actlow,count);

parameter n = 7;

    output reg [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;

    // Increment count on clock
    always @(actlow or posedge clk or negedge rst_n)
    begin
       if (actlow == 0)
       begin
           if (rst_n==0) 
          count = startc;
       else if (count==endc) count=startc;
           else count = count - 1;
       end
    end
endmodule

module Init(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;

    output wire [n:0] count;
    input  [n:0] startc;
    input  [n:0] endc;
    input clk;
    input rst_n;
    input actlow;
generate
    initial
    begin
        if(startc>endc)
        nbitDownCounter c(startc, endc, C_t,rst_t,actlow,count);
    end
endgenerate
endmodule

module Testbench;

    reg [7:0] startc, endc;
    reg C_t, rst_t;
    reg actlow;
    wire [7:0] outc;

    initial
    begin

    //case 0
    startc <= 8'b00000011; endc <= 8'b0000001;
    //Init i(startc,endc,C_t,rst_t,actlow,count);
    actlow<=0;
    C_t <=1; rst_t <=0;
    #1 $display("count = %b",outc );
    //case1

    rst_t<=1;C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );

    //Case3
    C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );
    //Case3
    C_t<=0;C_t<=1;
    #1 $display("count = %b",outc );
    end
endmodule
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1 回答 1

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您试图在初始块中实例化您的模块，这是非法的。删除模块 Init 中的初始开始应该可以解决问题。看看这个页面的例子：http ://asic-soc.blogspot.de/2012/06/verilog-hdl-generate-blocks.html

于 2014-02-14T09:07:37.783 回答