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我想使用计数器产生延迟，实际上在这里我使用计数器在每个 1 位传输后产生延迟，以便更好地理解 SPI（串行）LCD 与它连接的 fpga 引脚的外部。因此，我创建了一个移位寄存器，它先移位 1 位，然后给出延迟，然后是下一位（位延迟位延迟 ..）。

这是我的计数器代码：

module spidelay(
  input  wire clk,
  input  wire enb,
  output reg  sclkout
);
  reg [23:0] stmp;

  always @(posedge clk) begin
    if ( enb == 1 ) begin
      stmp = stmp+1;
      if( stmp[23] == 1 ) begin
        sclkout = 1'b1;
        stmp    = 24'b0;
       end
    end
    else begin
      stmp    = 24'b0;
      sclkout = 1'b0;
   end
 end
endmodule

朋友，但问题是我不知道如何在内部启用/启动计数器always block我的意思是我不知道如何在我们想要始终在内部产生延迟的行开始/启用计数器。

现在这是我想在特定行中产生延迟的顶级模块的代码--->>

 module Nokia_LCD(input clk,input switch,output OUT,output reset,inout sck,output cs);  
     wire clk;//On Board Clock
     wire switch;//Switch For RESET
     integer i;
     integer z;//Used for, for loop for generating delay
     reg signed OUT;//OUT for sending Data serially to LCD
     reg reset=1'b1;//To Reset LCD
     wire sck; //We select sck as inout because it taking input from counter Instance and then gives output to LCD..
     reg cs; //Chip select pin of lcd always set to zero 
     reg signed[8:0]out;//Register for Storing value of OUT
     reg [5:0]state =6'b000000; //Initialize states to Zero
     reg [7:0]finder; //Finder finds the state that was last present in it so that by this we again go to that state sequentially 
     reg [7:0]font[1:0][5:0];//2-D Array of 8 Bit For Font 
     reg [23:0]stmp=24'b00000_00000_00000_00000_0000;
     reg enb;
     wire sclkout;

     counter count1(clk,sck);//Instance of Counter1 for SCK Clock
     spidelay count2(clk,enb,sclkout);

    always@(posedge clk)
    begin
    case (state)

      /* Lcd Initialization starts from here*/
           6'b000000 : begin
           finder=8'b00000000;
           cs=1'b0;
             out=9'b0_00010001; //Using Command SLEEPOUT (Hex 0x11) - Exits LCD sleep mode
             state=6'b010001; 
           end

           6'b000001: begin
           finder=8'b00000001;
           cs=1'b0; 
             out=9'b0_00000011; //Using Command BSTRON (Hex 0x03) - Turns on booster voltage     
             state =6'b010001; 
             end 

      /******************************************************************************************************************/
      /************************************ State for SPI Data Transfer & Delay *****************************************/
      /******************************************************************************************************************/ 
           6'b010001:begin

           //We Use finder to find the state from which it Comes...

             if(finder==8'b00000000) //for 0
                     begin:close1         
                     cs=1'b0;
            for(i=0;i<=8;i=i+1)
            begin
            out=out<<<1;
            OUT=out[8];
              enb=1'b1;  <<<<<<<-----|This is the place where I want it to enable counter and it must stop here  for counting and during this time it not move for othe count of for loop......


            if(stmp[23]==1'b1)
             begin
             disable close1;
             end
             end
             state=6'b000001;//Go to State 000001(BSTRON)
         end    




       endcase  

     end //Always end


    endmodule

必须注意的是，朋友们我对其进行了编辑，以便专注于错误点....所以如果您在某个地方发现语法错误，请忽略它，但请帮助我并给出一些建议以在 Toppest 模块上产生延迟通过给出 enb=1'b1 ........

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1 回答 1

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建议使用<=内部边缘触发块always @( posedge ...

您提到延迟，我假设您指的是延迟固定数量的时钟周期。在这种情况下，这就是您所做的，您只是在不满足计数器要求时没有重置 sclkout。

if ( enb == 1 ) begin
  sclkout <= 1'b0;  //Reset by default
  stmp    <= stmp+1;

  if( stmp[23] == 1 ) begin //Counter target
    sclkout <= 1'b1;
    stmp    <= 24'b0;
  end
end
else begin
  //...

或者添加一个else

if ( enb == 1 ) begin
  if( stmp[23] == 1 ) begin //Counter target
    sclkout <= 1'b1;
    stmp    <= 24'b0;
  end
  else begin
    sclkout <= 1'b0;  //Reset by default
    stmp    <= stmp+1;
  end
end
else begin
  //...

注意：输入是隐含的连线，如果您不想，则不必编写它。input wire clk是一样的input clk。

我还将在您的比较中添加一个宽度，即== 1'b0代替== 0，否则稍后在您的设计流程中，您将收到宽度不匹配警告。

更新
根据评论中添加的信息，要求计数器在何时停止enb==1'b1，我假设它代表“启用栏”

always @ (posedge clk) begin
  if ( enb == 1'b0 ) begin
   // When enable bar is low this is Active
   stmp    <= stmp + 1'b1;
   // etc ...
  end
  //else begin
  //  Do Nothing (hold state)
  //end
end
于 2013-12-03T10:28:10.463 回答