makefile - Assigning variable value inside recipe in GNUMakefile

Question

I'm not able to assign values to variable inside recipe.

debug: $(EXEC)
    CFLAGS+=-g -DDEBUG
    make $(EXEC) 
$(EXEC): example.c
   cc $(CFLAGS) -o example example.c

Output:

CFLAGS+=-g -DDEBUG 
/bin/sh: 1: CFLAGS+=-g: not found
make: *** [debug] Error 127

Answer 1

A make recipe is not makefile syntax, it's a shell script. It's passed to the shell, which is a subprocess and (in UNIX/POSIX) there's no way for a subprocess to modify its parent.

There's a lot wrong here. First, you should never use make to run make recursively, always use $(MAKE).

Second, you have a useless recursion here. debug depends on $(EXEC), so before the debug recipe is run make will build $(EXEC). Then in the debug recipe you will recursively invoke make to build $(EXEC) again, but this will do nothing because $(EXEC) is already built.

You don't need the recursion, and you can use target-specific variables to do what you want:

debug: CFLAGS += -g -DDEBUG
debug: $(EXEC)

$(EXEC): example.c
        $(CC) $(CFLAGS) -o $@ $<