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首先，我对 verilog 以及 ise webpack 的工作原理几乎是全新的。所以我正在尝试编写一些代码，它将接受输入方波到 basys2 fpga 板上的引脚 B2。我遇到的问题是，当我生成程序文件（.bit）并将其加载到板上时，所有 LED 都亮着。在文件形成过程中我没有收到任何错误，并且我理解代码对于我想要它做的事情是正确的。我收到有关 ff/latch 微调的警告，以及“信号不完整。信号不驱动任何负载”。我已经在这里发布了代码以及 ucf 文件

module IRVFILE(input clk, signal, 

                    output LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0 
                          );

parameter tenth= 5000000; // tenth of a second

reg[24:0]count;                //0-24bts

reg[24:0]displaycount;

reg[24:0]timer;

reg [7:0] leddata;


assign LED7= leddata[7];

assign LED6= leddata[6];

assign LED5= leddata[5];

assign LED4= leddata[4];

assign LED3= leddata[3];

assign LED2= leddata[2];

assign LED1= leddata[1];

assign LED0= leddata[0];

//////////////////////////////////////////////////////////////////////////////////

initial begin

    count <=0;
    timer <=tenth;

     displaycount =0;
     leddata = 0;

end

always@(posedge clk) begin

if(timer>=1)begin
    if(signal==1)begin

        count = count + 1;

        end
    end 
else begin
    timer <= tenth;

    displaycount <=count;

    count =0;
     leddata <=0;

end

if (displaycount >= 20) begin
    leddata[0]<=1;
    end

if (displaycount >=30)begin
    leddata[1]<=1;
    end

if (displaycount >=40)begin
    leddata[2]<=1;
    end

if (displaycount >=50)begin
    leddata[3]<=1;
    end

if (displaycount >=60)begin
    leddata[4]<=1;
    end

if (displaycount >=70)begin
    leddata[5]<=1;
    end

if (displaycount >=80)begin
    leddata[6]<=1;
    end

if (displaycount >=90)begin
    leddata[7]<=1;
    end

end
endmodule


ucf:

# clock pins for Basys2 Board
#NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK
#NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK
#NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "uclk" CLOCK_DEDICATED_ROUTE = FALSE;

NET "clk" LOC = B8;

## Pin assignment for EppCtl
## Connected to Basys2 onBoard USB controller
#NET "EppAstb" LOC = "F2"; # Bank = 3
#NET "EppDstb" LOC = "F1"; # Bank = 3
#NET "EppWR"       LOC = "C2"; # Bank = 3

#NET "EppWait" LOC = "D2"; # Bank = 3
#NET "EppDB<0>" LOC = "N2"; # Bank = 2
#NET "EppDB<1>" LOC = "M2"; # Bank = 2
#NET "EppDB<2>" LOC = "M1"; # Bank = 3
#NET "EppDB<3>" LOC = "L1"; # Bank = 3
#NET "EppDB<4>" LOC = "L2"; # Bank = 3
#NET "EppDB<5>" LOC = "H2"; # Bank = 3
#NET "EppDB<6>" LOC = "H1"; # Bank = 3
#NET "EppDB<7>" LOC = "H3"; # Bank = 3


# Pin assignment for DispCtl
# Connected to Basys2 onBoard 7seg display
#NET "segments<0>" LOC = "L14"; # Bank = 1, Signal name = CA
#NET "segments<1>" LOC = "H12"; # Bank = 1, Signal name = CB
#NET "segments<2>" LOC = "N14"; # Bank = 1, Signal name = CC
#NET "segments<3>" LOC = "N11"; # Bank = 2, Signal name = CD
#NET "segments<4>" LOC = "P12"; # Bank = 2, Signal name = CE
#NET "segments<5>" LOC = "L13"; # Bank = 1, Signal name = CF
#NET "segments<6>" LOC = "M12"; # Bank = 1, Signal name = CG
#NET "segments<0>" LOC = "N13"; # Bank = 1, Signal name = DP

#NET "digit<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
#NET "digit<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
#NET "digit<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
#NET "digit<0>" LOC = "F12"; # Bank = 1, Signal name = AN0

# Pin assignment for LEDs

NET "LED0" LOC = "m5" ; # Bank = 3, Signal name = LD7

NET "LED1" LOC = "m11" ; # Bank = 2, Signal name = LD6

NET "LED2" LOC = "p7" ;  # Bank = 2, Signal name = LD5

NET "LED3" LOC = "p6" ;  # Bank = 2, Signal name = LD4

NET "LED4" LOC = "n5" ; # Bank = 2, Signal name = LD3

NET "LED5" LOC = "n4" ; # Bank = 3, Signal name = LD2

NET "LED6" LOC = "p4" ; # Bank = 2, Signal name = LD1

NET "LED7" LOC = "g1" ;  # Bank = 2, Signal name = LD0

# Pin assignment for SWs
#NET "swF" LOC = "N3";  # Bank = 2, Signal name = SW7
#NET "sw<6>" LOC = "E2";  # Bank = 3, Signal name = SW6
#NET "sw<5>" LOC = "F3";  # Bank = 3, Signal name = SW5
#NET "sw<4>" LOC = "G3";  # Bank = 3, Signal name = SW4
#NET "sw<3>" LOC = "B4";  # Bank = 3, Signal name = SW3
#NET "sw<2>" LOC = "K3";  # Bank = 3, Signal name = SW2
#NET "sw<1>" LOC = "L3";  # Bank = 3, Signal name = SW1
#NET "sw<0>" LOC = "P11";  # Bank = 2, Signal name = SW0

#NET "PB_F" LOC = "A7";  # Bank = 1, Signal name = BTN3
#NET "push" LOC = "M4";  # Bank = 0, Signal name = BTN2
#NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1
#NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0
#NET "line1" LOC = "B9";
#NET "line2" LOC = "C10";
#NET "line3" LOC = "A3";
#NET "line4" LOC = "B5";
#NET "signal" CLOCK_DEDICATED_ROUTE = FALSE;

## Loop back/demo signals
## Pin assignment for PS2
#NET "PS2C"    LOC = "B1"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2C
#NET "PS2D"    LOC = "C3"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2D

# Pin assignment for VGA
#NET "HS"   LOC = "J14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = HSYNC
#NET "VS"   LOC = "K13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = VSYNC

#NET "OutRed<2>"  LOC = "F13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED2
#NET "OutRed<1>"  LOC = "D13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED1
#NET "OutRed<0>"  LOC = "C14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED0
#NET "OutGreen<2>"  LOC = "G14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN2
#NET "OutGreen<1>"  LOC = "G13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN1
#NET "OutGreen<0>"  LOC = "F14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN0
#NET "OutBlue<2>"  LOC = "J13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU2
#NET "OutBlue<1>"  LOC = "H13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU1

## Loop Back only tested signals
//  | PULLDOWN ; # Bank = 1, Signal name = JA1

NET "signal" LOC = B2;

#NET "two" LOC = C5;

##NET "two" DRIVE = 2;
// | PULLDOWN ; # Bank = 1, Signal name = JA2
#NET "three" LOC = B5;
#NET "four" LOC = J3;
#NET "enA" LOC = A3;
#NET "three" DRIVE = 2;
#NET "enB" LOC = B6;#  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA3
#NET "PIO<75>" LOC = "B5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA4
#
//  | PULLDOWN ; # Bank = 1, Signal name = JB1

#NET "four" DRIVE = 2;
//  | PULLDOWN ; # Bank = 1, Signal name = JB2

#NET "one" DRIVE = 2;
#NET "PIO<78>" LOC = "C5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB3
#NET "PIO<79>" LOC = "B7"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB4
#
#NET "phone" LOC = C6; // | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC1
#NET "phtwo" LOC = B2; // | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC4
#
#NET "stall" LOC = B9; //  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD1
#NET "stallB" LOC = A9; //  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD2
#NET "PIO<86>" LOC = "C13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD3
#NET "cmp[0]" LOC = D12; //  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD4
#NET "cmp[1]" LOC = C13;
#NET "cmp[2]" LOC = A13;

#NET "fire" LOC = A10;
4

2 回答 2

1

使用提供的 Verilog 代码，if(timer>=1)将始终正确。因此，if语句的结构将永远不会更新displaycount，这反过来又会阻止leddata表单被更新。合成时，您的所有 Verilog 代码都将被优化，因为不会发生对寄存器的更改。

Verilog 需要重新编码。在模拟器中运行 Verilog（选择模拟器http://en.wikipedia.org/wiki/List_of_Verilog_simulators或尝试http://www.edaplayground.com/home）。在仿真中工作后，尝试在 FPGA 中运行代码。

最好的猜测期望的结果看起来更像如下：（http://www.edaplayground.com/s/6/189）

always@(posedge clk or negedge rst_n) begin : dff
    if( !rst_n ) begin : reset
        counting <= 1'b0;
        count    <= 25'b0;
        leddata  <= 8'b0;
    end : reset
    else begin
        counting <= signal;
        count    <= signal ? (count+1'b1) : 25'b0;
        leddata  <= next_leddata;
     end
end : dff

always @* begin : calc_leddata
    if ( !counting || signal ) begin : keep
        next_leddata = leddata;
    end : keep
    else begin : calc_new
        next_leddata = 8'b0;
        if (count >=20) next_leddata[0] = 1'b1;
        if (count >=30) next_leddata[1] = 1'b1;
        if (count >=40) next_leddata[2] = 1'b1;
        if (count >=50) next_leddata[3] = 1'b1;
        if (count >=60) next_leddata[4] = 1'b1;
        if (count >=70) next_leddata[5] = 1'b1;
        if (count >=80) next_leddata[6] = 1'b1;
        if (count >=90) next_leddata[7] = 1'b1;
    end : calc_new
end : calc_leddata
于 2013-09-26T23:18:38.630 回答
1

我在您的代码中看到的是您正在使用一个不可综合的初始语句，并且我看到您想将其用作重置（以设置默认值）。我建议您删除它并在 always 语句中使用重置。我放了一个异步重置来让你控制你什么时候想要重置你的设计，它也可以是同步重置。

//删除初始块

initial begin

    count <=0;
    timer <=tenth;

     displaycount =0;
     leddata = 0;

end 

always@(posedge clk, posedge a_rst) begin //This is an async reset which 
  if (a_rst) begin
    count <= 0;
    timer <= tenth;
    displaycount <=0;
    leddata <= 0;
  end
 else begin
   //Put the rest of the code here
 end

另外我建议您在描述时钟触发逻辑时，使用非阻塞分配，不要在同一个始终进程中组合阻塞和非阻塞。

例如在这行代码中：count = count + 1; //改为非阻塞（即count <= count + 1;）

我建议你阅读这篇关于阻塞和非阻塞分配的论文。

http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

让我知道情况如何，如果您需要更多帮助

于 2013-09-13T15:53:01.530 回答