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I have a design were I'm writing/reading to/from a RAM and perform some computation on the read values. In some cases, I read values from RAM locations where I haven't written anything to yet. This is intentional because in the cases where this happens, the uninitialized values don't affect the computation: in these cases, the uninitialized values are multiplied with 0.

However, multiplying an unsigned/signed type which contains 'U' bits results in a "don't care" output (i.e. all bits of the multiplication output are 'X') even if the other operand is 0. Therefore, I can't check the final computation output in my testbench because it becomes "don't care" (it seems like "don't care" outputs are interpreted as 0).

To avoid this problem, I wrote a function that resolves any 'U' or 'X' bits in a std_logic_vector to '0'. The functions looks as follows

function f(x : std_logic_vector) return std_logic_vector is
  variable y : std_logic_vector (x'range);
begin
  y := x;
  -- pragma synthesis off
  for i in 0 to x'length-1 loop
    case x(i) is
      when 'U' | 'X' => y(i) := '0';
      when others    => y(i) := x(i);
    end case;
  end loop;  -- i
  -- pragma synthesis on
  return y;
end;

Now I'd like to expand the function by not only setting 'X' and 'U' bits to '0' but to randomly set them to either '0' or '1'. I've tried using the uniform function within f. The problem is that when I define the two seeds within the function, that each time the function f is called it returns the same std_logic_vector (when it is given the same std_logic_vector). As I take it from the uniform function description, I should pass the two seeds from outside the function f because they are modified by the uniform function for the next call to uniform.

Is there a possibility how this can be achieved using a function?

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3 回答 3

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作为开源 VHDL 验证方法的一部分，这里有一个非常好的随机库。这里有描述和下载链接。

http://www.synthworks.com/blog/osvvm/

它允许您随机化不仅仅是浮点数的简单均匀分布。以及将您与您注意到的状态存储问题隔离开来。

关于你的具体情况：

正如我从统一函数描述中得出的那样，我应该从函数 f 外部传递两个种子，因为它们被统一函数修改以用于下一次调用统一。

是的你应该。像这样：

PROCESS
  VARIABLE seed1, seed2: positive; -- Seed and state values for random generator
  VARIABLE rand: real;             -- Random real-number value in range 0 to 1.0
BEGIN
    UNIFORM(seed1, seed2, rand);

因此，在您的情况下，您还必须将这些“状态”变量传入（传出）您的函数——这实际上意味着它必须是一个过程。

或者使用上面链接的 OSVVM 库，它允许您拥有一个受保护类型的共享变量，您可以在各个地方使用它。这会将自己的状态保持在受保护类型的“内部”。

于 2013-05-07T14:20:05.437 回答
1

我可以使用函数来实现这一点还是必须使用过程？

函数不允许参数为 inout、指针或受保护类型。这限制了你的选择。OSVVM 的 randompkg 使用受保护的类型来隐藏种子并使用不纯函数来访问它。它很容易使用。只需从http://www.synthworks.com/downloads下载软件包 并查看 RandomPkg_user_guide.pdf。

你可能会得到你想要做的工作，然而，这将是一个挑战。您可以在包中定义一个信号或一对信号并使用不纯函数（YMMV，我只在受保护类型中使用了不纯函数）。您可以在信号声明中初始化种子。

即使使用 OSVVM，您也需要使用不纯函数并将随机化对象声明为共享变量。

吉姆

于 2013-05-09T21:15:33.990 回答
0

关于从 VHDL 组件打印实例名称：...我的大部分工作都是使用免费的 VHDL 模拟器 GHDL 完成的。它有一个简单但功能强大的 c 接口。随机可以使用c代码完成：... http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_func_rand.html

于 2014-12-27T15:46:42.500 回答