我知道闩锁在硬件和 Verilog 编码中是不受欢迎的。但是,我有时会遇到无法避免闩锁的情况。例如,在这两种情况下:
always @ (*)
begin
random_next = random; //default state stays the same
count_next_r = count_r;
random_next = {random[28:0], feedback}; //**shift left the xor'd every posedge clock
if (count_r == 30) //if all 30 bits are shifted into register
begin
count_next_r = 0;
random_done = random; //assign the random number to output after 13 shifts
end
else
count_next_r = count_r + 1;
这random_done
是一个闩锁。我看不到任何其他写这个的方式。我只希望random_done
在 30 个班次后有数据random
。如果我以这种方式实现它,我会收到闩锁的警告,并且它无法正常工作。
同样,在下面的代码中:
always @ (*)
begin
state_next = state_reg; //default state stays the same
count_next = count_reg;
sel_next = sel;
case(state_reg)
idle:
begin
//DISPLAY HI HERE
sel_next = 2'b00;
if(start)
begin
count_next = random_done; //get the random number from LFSR module
state_next = starting;
end
end
starting:
begin
if(count_next == 750000000) // **750M equals a delay of 15 seconds. 8191 for simulation
begin //and starting from 'rand' ensures a random delay
outled = 1'b1; //turn on the led
state_next = time_it; //go to next state
end
else
begin
count_next = count_reg + 1;
outled = 1'b0;
end
end
time_it:
begin
sel_next = 2'b01; //start the timer
state_next = done;
end
done:
begin
if(stop)
begin
sel_next = 2'b10; //stop the timer
outled = 1'b0;
end
end
endcase
从上面的代码中,有问题的部分是这样的:
done:
begin
if(stop)
begin
sel_next = 2'b10; //stop the timer
outled = 1'b0;
end
这里outled
被检测为一个锁存器,在执行过程中我被警告了这一点。我只是想让 LED 在按下停止位时变低。
我怎样才能避免这些闩锁?