我编写了一个 VHDL 代码来实现 PWM 控制器的功能。我已经模拟成功,结果符合预期。我还检查了合成的语法,但它显示了任何错误。当我使用 XILINX ISE 12.4 合成它时,它没有合成并且错误状态
“错误:Xst:827 - 第 67 行:信号 tmp_PC 无法合成,同步描述错误。当前软件版本不支持您用于描述同步元素(寄存器、内存等)的描述样式。”
--library UNISIM;
--use UNISIM.VComponents.all;
entity CONTROLLER is
PORT(
CLK: IN STD_LOGIC;
VOUT: IN STD_LOGIC;
M1: OUT STD_LOGIC:='0';
M2: OUT STD_LOGIC:='0'
);
end CONTROLLER;
architecture Behavioral of CONTROLLER is
SIGNAL VREF: STD_LOGIC_VECTOR(7 DOWNTO 0):="01000000";
SIGNAL V_ERR: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL PWM: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL PWM_NEW: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL COUNT: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL COUNT2: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL TEMP1: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL TEMP2: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL TEMP3: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL FEED_BACK: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL REG: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL PWM_COUNT: STD_LOGIC_VECTOR(7 DOWNTO 0):="10000000";
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK) AND COUNT2<"10000000")THEN
COUNT <= COUNT+'1';
END IF;
IF(RISING_EDGE(CLK) AND COUNT2>="10000000")THEN
COUNT <= COUNT+'1';
END IF;
IF (COUNT>"00000101" AND COUNT<"01111000") THEN
IF(RISING_EDGE(CLK))THEN
IF (VOUT='0') THEN
FEED_BACK<= FEED_BACK+'1';
END IF;
END IF;
END IF;
IF (COUNT>"01111000" AND COUNT<"01111100")THEN
REG<=FEED_BACK;
TEMP1<=VREF-REG;
IF(TEMP1>"01000000") THEN
TEMP2<=TEMP1+"11111111";
V_ERR<=TEMP2+'1';
END IF;
IF (TEMP1<"01000000") THEN
V_ERR<=TEMP1;
END IF;
PWM<=V_ERR+VREF;
IF (PWM>"11000000")THEN
PWM<="11000000";
IF(PWM<"00001010")THEN
PWM<="00001010";
END IF;
END IF;
END IF;
PWM_NEW<= PWM;
IF (RISING_EDGE(CLK))THEN
IF(COUNT="01111111")THEN
COUNT<="00000000";
FEED_BACK<="00000000";
END IF;
END IF;
IF(RISING_EDGE(CLK))THEN
COUNT2 <= COUNT2+ '1';
END IF;
IF(COUNT>"00000000" AND COUNT<("00000010"))THEN
IF(RISING_EDGE(CLK)) THEN
M1<='0';
M2<='0';
END IF;
END IF;
IF(COUNT>("00000010") AND COUNT<("00000010"+PWM_NEW))THEN
IF(RISING_EDGE(CLK)) THEN
M1<='1';
M2<='0';
END IF;
END IF;
IF(COUNT>("00000010"+PWM_NEW) AND COUNT<("00000100"+PWM_NEW))THEN
IF ( RISING_EDGE(CLK)) THEN
M1<='0';
M2<='0';
END IF;
END IF;
IF(COUNT>("00000100"+PWM_NEW) AND COUNT<("10000000"))THEN
IF (RISING_EDGE(CLK)) THEN
M1<='0';
M2<='1';
END IF;
END IF;
IF (COUNT=("10000000"))THEN
IF (RISING_EDGE(CLK)) THEN
COUNT2<="10000001";
END IF;
END IF;
END PROCESS;
end Behavioral;`
我尝试查找错误消息并得到不同的答案。出现的可能原因1:不符合综合模板的“IF”嵌套不当。2:使用“risisng_edge(clk)”而不是通常的“(clk'event and clk='1')”。
我仍然不完全确定可能是什么问题。如果有人可以提出我忽略的可能错误,那将非常有帮助。