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我有一个核心(用 VHDL 编写),它有一个 5 级管道,我使用 ModelSim 进行仿真。我对 clk 应用了一些错误,以查看它对内核的影响。
我需要查看管道阶段是否正常运行?是否可以在 ModelSim 中看到流水线阶段?
我将不胜感激任何建议!