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我正在尝试将 2 个输出加在一起，并在 7 段显示器上的第三/第四显示器中显示它们的结果。每个输出分别显示在它们自己的段中。第四个显示为两位数（最大值为 14，最小值为 0）。我收到一条错误消息，指出我需要编写“添加”案例的所有实例。不知道从这里去哪里。任何帮助表示赞赏。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  Midterm2_Q2_4369 IS
PORT (

SW: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SW0: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

ADD: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y0: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y1: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

Y2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END Midterm2_Q2_4369;
ARCHITECTURE MUX8 OF Midterm2_Q2_4369 IS 
BEGIN
PROCESS (SW,SW0,ADD)
BEGIN
CASE SW IS
WHEN "000" => Y <= "0000001";

WHEN "001" => Y <= "1001111";

WHEN "010" => Y <= "0010010";

WHEN "011" => Y <= "0000110";

WHEN "100" => Y <= "1001100";

WHEN "101" => Y <= "0100100";

WHEN "110" => Y <= "0100000";

WHEN "111" => Y <= "0001111";
END CASE;

CASE SW0 IS
WHEN "000" => Y0 <= "0000001";

WHEN "001" => Y0 <= "1001111";

WHEN "010" => Y0 <= "0010010";

WHEN "011" => Y0 <= "0000110";

WHEN "100" => Y0 <= "1001100";

WHEN "101" => Y0 <= "0100100";

WHEN "110" => Y0 <= "0100000";

WHEN "111" => Y0 <= "0001111";
END CASE;

CASE ADD IS
WHEN "0000000" => Y1 <= "0000001"; --0

WHEN "0000001" => Y1 <= "1001111"; --1

WHEN "0000010" => Y1 <= "0010010"; --2

WHEN "0000011" => Y1 <= "0000110"; --3

WHEN "0000100" => Y1 <= "1001100"; --4

WHEN "0000101" => Y1 <= "0100100"; --5

WHEN "0000110" => Y1 <= "0100000"; --6

WHEN "0000111" => Y1 <= "0001111"; --7

WHEN "0001111" => Y1 <= "0000000"; --8

WHEN "0010111" => Y1 <= "0000100"; --9
     --8421421
WHEN "0011111" => Y2 <= "1001111"; --(1)0

WHEN "0100111" => Y2 <= "1001111"; --(1)1

WHEN "0101111" => Y2 <= "1001111"; --(1)2

WHEN "0110111" => Y2 <= "1001111"; --(1)3

WHEN "0111111" => Y2 <= "1001111"; --(1)4--

WHEN "1000111" => Y2 <= "1001111"; --(1)5

WHEN "1001111" => Y2 <= "1001111"; --(1)6

WHEN "1010111" => Y2 <= "1001111"; --(1)7--

WHEN "1011111" => Y2 <= "1001111"; --(1)8

WHEN "1100111" => Y2 <= "1001111"; --(1)9
END CASE;

END PROCESS;
END MUX8;
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1 回答 1

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在 VHDL 中使用 acase时，必须涵盖所有情况。SW因为，SW0而且ADD都是，您还必须涵盖所有元案例，例如“ UUUUUUUU std_logic_vector”等。最简单的方法是使用others.

例如。SW0 涵盖了所有“真实”情况，但您还必须涵盖只能在模拟中出现的值，因此请提供一条方便的消息：

CASE SW0 IS
  WHEN "000" => Y0 <= "0000001";
  WHEN "001" => Y0 <= "1001111";
  WHEN "010" => Y0 <= "0010010";
  WHEN "011" => Y0 <= "0000110";
  WHEN "100" => Y0 <= "1001100";
  WHEN "101" => Y0 <= "0100100";
  WHEN "110" => Y0 <= "0100000";
  WHEN "111" => Y0 <= "0001111";
  when others => report "Meta value detected" severity warning;-- simulation only case
END CASE;

SW您还必须确保涵盖所有ADD情况

于 2021-11-18T20:28:43.333 回答