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--sequence 011 -non overlapping
library ieee;
use ieee.std_logic_1164.all;

entity Q2mealy_011_NOL is
  port(x, clk, reset: in std_logic;
       z: out std_logic);
end Q2mealy_011_NOL;

architecture mealy_011_NOL of Q2mealy_011_NOL is

  type statetype is (a, b, c);
  signal pr_st, nx_st: statetype;

begin
  nsl: process(pr_st, x)  --next state logic process
  begin
    case pr_st is
    when a =>                      --a means 00 state
      if x = '0' then nx_st <= b;
      else nx_st <= a;
      end if;

    when b =>                      --b means 01 state
      if x = '1' then nx_st <= c;
      else nx_st <= b;
      end if;

    when c =>                      --c means 10 state
      if x = '1' then nx_st <= a;
      else nx_st <= a;
      end if;

    when others =>
      nx_st <= a;
    end case;
  end process nsl;

  FF: process(clk, reset)  --flipflop process
  begin
    if (reset = '1') then pr_st <= a;
    elsif (clk'event and clk = '1') then
      pr_st <= nx_st;
    end if;
  end process FF;

  --Output Logic
  z <= '1' when ((pr_st = c) and (x = '1')) else '0';

end mealy_011_NOL;

此 VHDL 代码没有任何错误。但是，我需要知道如何将有限状态机（011-非重叠）的这种行为模型 VHDL 代码转换为数据流模型 VHDL 代码（将行为模型转换为数据流模型）。

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