我正在创建一个 Alu，这是我的代码。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is port (
entrada: in std_logic_vector(11 downto 0);
S: in std_logic_vector(3 downto 0);
load : in std_logic;
O: out std_logic_vector(12 downto 0)
);
end alu;
architecture arc_alu12 of alu is
component sumador12bits
port (a, b: in std_logic_vector(11 downto 0); c: out std_logic_vector(12 downto 0));
end component;
signal sa, sb, A, aux: std_logic_vector(11 downto 0):="000000000000";
signal sr: std_logic_vector(12 downto 0);
begin
guarda_registro: process (load) begin
if load = '1' then
A <= entrada;
end if;
end process;
sss: sumador12bits port map(sa, sb, sr);
selector: process(S) begin
case S is
when "0000" =>
sa <= "0000"&A(7 downto 0);
sb <= "0000"&entrada(7 downto 0);
when "0001" =>
sa <= "0000"&A(7 downto 0);
aux <= "0000"&entrada(7 downto 0);
sb<= (not aux)+1;
when "0010" =>
sa <= A;
sb <= "000000000001";
when "0011" =>
sa <= A;
sb <= "111111111111";
when "0100" =>
sa <= entrada;
sb <= "000000000001";
when "0101" =>
sa <= entrada;
sb <= "111111111111";
when "0110" =>
sa <= A;
sb <= entrada;
when "0111" =>
sa<=A;
sb<= (not entrada)+1;
when "1000" =>
sr <= '0'&(A and entrada);
when "1001" =>
sr <= '0'&(A or entrada);
when "1010" =>
sr <= '0'&(A xor entrada);
when "1011" =>
sr <= '1'¬ A;
when "1100" =>
sa <= not A;
sb <= "000000000001";
when others => sr<= "0000000000000";
end case;
end process;
O <= sr;
end arc_alu12;
但我收到此消息错误：
@A: BN321 |在网络 O[0] 上找到多个驱动程序（在视图中：work.alu(arc_alu12)）；如果一个驱动器是常数（真或假），请使用 Resolve Mixed Drivers 选项将网络连接到 VCC 或 GND。
连接1：方向是（输出）pin:s inst:sss.FA1.ss1 of work.semisumador(syn_black_box)
连接 2：方向为（输出） pin:Q[0] inst:selector.sr[0] of PrimLib.latr(prim)
错误 - BN314 :"e:\lscc\diamond\3.12\bin\nt64\alucode.vhd":6:7:6:9|Net O[0] (in view: work.alu(arc_alu12)) 有多个驱动程序