riscv - 从零增加 AsIDBits

Question

我想将 Rocket-Chip 中的 AsIDBit 数量从零增加到八，并且想知道如何实现。

瓦片/BaseTile.Scala

trait HasNonDiplomaticTileParameters {
    implicit val p: Parameters
    //...
    def asIdBits: Int = p(ASIdBits)
    //...
}

https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala

我想实现一个类似于这里定义的类

子系统/Config.Scala

//...
class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
    case RocketTilesKey => up(RocketTilesKey, site) map { r =>
        r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(divSqrt = false))))
    }
})

class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
    case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
})

class WithSynchronousRocketTiles extends Config((site, here, up) => {
    case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
        r.copy(crossingType = SynchronousCrossing())
    }
})
//...

https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/subsystem/Configs.scala

我试着这样做

class SetAsIDBits(n: Int) extends Config(
    (site, here, up) => {
        case ASIdBits => n
    }
)

但得到下面列出的错误

Configs.scala:272:10: not found: value ASIdBits    
[error]     case ASIdBits => n        
[error]          ^             
[error] one error found   
[error] (Compile / compileIncremental) Compilation failed  

Answer 1

我认为这只是表明ASIdBits没有定义。您可以尝试导入它：

import freechips.rocketchip.rocket.ASIdBits