vhdl - vhdl 无效的内存访问（悬空访问或堆栈大小太小）

Question

我正在尝试重新创建一个红绿灯。而且似乎我的程序中有某种循环，因为每当我运行我的测试平台时都会出现此消息。我知道测试台中的循环没问题，至少不是主要问题，因为一旦我将其注释掉，错误消息又出现了。一旦我注释掉ampel（红绿灯），错误就不再存在了。所以我的猜测是我的ampel实体有问题，但我找不到它是什么。

这里的代码：

library ieee;
use ieee.std_logic_1164.all;

entity ampel is

    port (
      clk, reset : in std_logic;
      rot, gelb, gruen : out std_logic_vector(3 downto 0)
    );
  end ampel;

architecture rtl of ampel is
    
type t_zustand is (a,b,c,d,e,f,g,h);

signal zustand : t_zustand;
signal timer : integer;

begin
rot <= "1111";
    process is
    begin
        wait on clk until clk = '1';
            timer <= timer + 1;
            if reset = '0' then
                zustand <= a;
                rot <= "1111";
                gelb <= "0000";
                gruen <= "0000";
                timer <= 2;
            else 
                case zustand is
                    when a => 
                        rot <= "1111"; 
                        gelb <= "0000"; 
                        gruen <= "0000"; 
                        if timer = 5  then
                            zustand   <= b;
                        end if;
                        
                    when b => 
                        rot <= "0101"; 
                        gelb <= "1010"; 
                        gruen <= "0000";
                        if timer = 10 then
                            zustand   <= c;
                        end if;
                        
                    when c => 
                        rot <= "0101";
                        gelb <= "0000"; 
                        gruen <= "1010";
                        if timer = 40 then
                            zustand   <= d;
                        end if;
                        
                    when d =>
                        rot <= "0101";
                        gelb <= "1010";
                        gruen <= "0000";
                        if timer = 45 then
                            zustand   <= e;
                        end if;
                        
                    when e => 
                        rot <= "1111";
                        gelb <= "0000";
                        gruen <= "0000";
                        if timer = 50 then
                            zustand   <= b;
                        end if;
                        
                    when f => 
                        rot <= "1010";
                        gelb <= "0101";
                        gruen <= "0000";
                        if timer = 55 then
                            zustand   <= b;
                        end if;
                        
                    when g => 
                        rot <= "1010";
                        gelb <= "0000";
                        gruen <= "0101";
                        if timer = 85 then
                            zustand   <= b;
                        end if;
                        
                    when h =>
                        rot <= "1010";
                        gelb <= "0101";
                        gruen <= "0000";
                        if timer = 90 then
                            zustand   <= b;
                        end if;
                        
                end case;
            end if;
    end process;
    
end rtl ;

测试台：

library ieee;
use ieee.std_logic_1164.all;

entity ampel_tb is
end ampel_tb;

architecture testbench of ampel_tb is

    component ampel is 
    port(
        clk, reset : in std_logic;
        rot, gelb, gruen : out std_logic_vector(3 downto 0)
    );
    end component;

signal clk, reset : std_logic;
signal rot, gelb, gruen : std_logic_vector(3 downto 0);

begin
   ampel0: ampel port map(clk => clk, reset => reset, rot => rot, gelb => gelb, gruen => gruen);
    
   process begin
        reset <= '0';
        clk <= '0';
        wait for 500 ms;
        clk <= '1';
        wait for 500 ms;
        reset <= '1';
        clk <= '0';
        wait for 500 ms;
        for I in 0 to 180 loop 
            clk <= '1';
            wait for 500 ms;
            clk <= '0';
            wait for 500 ms;
        end loop;
        assert false report "End of test";
        wait;
    end process;
   
end testbench;