vhdl - 高阻信号不进入测试台【VHDL】

Answer 1

在@BrianDrummond 和@Tricky 的评论的指导下，我可以发布我的问题的答案。问题的原因及其解决方法可以在问题下的评论中找到。

RAM_TB.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM_TB is
end entity;

architecture RAM_TB_arch of RAM_TB is
    component RAM 
    port (CLK : in std_logic; -- Clock
          R   : in std_logic; -- Reset
          WR  : in std_logic; -- Write
          AE  : in std_logic; -- Address saving in temp.    
          OE  : in std_logic; -- Signal about output word
          AD  : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data) 
    end component;
    constant T : time := 20 ns;
    
    signal CLK_TB, R_TB, WR_TB, AE_TB, OE_TB : std_logic;
    signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
    
    begin
        
        DUT : RAM port map (CLK_TB, R_TB, WR_TB, AE_TB, OE_TB, AD_TB);
        
        process
        begin
            CLK_TB <= '0';
            wait for T/2;
            CLK_TB <= '1';
            wait for T/2;
        end process;
        
        STIMULUS : process
        variable value : std_logic_vector(AD_TB'range) := X"FFFF";
        variable addr  : std_logic_vector(AD_TB'range) := X"0004"; 
        begin
            -- Test ZZZZ output of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '0'; -- No address 
            OE_TB <= '0'; -- No output
            wait for 2*T;
            Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
            
            -- Test input of AD
            R_TB  <= '0'; -- No reset
            WR_TB <= '0'; -- No write
            AE_TB <= '1'; -- Read address 
            OE_TB <= '0'; -- No output
            AD_TB <= addr; -- Address RAM(4)
            wait for T;
            WR_TB <= '1'; -- Write
            AE_TB <= '0'; -- Do not read address
            AD_TB <= value; -- Data to write
            wait for T;
            -- Test output of AD
            AD_TB <= "ZZZZZZZZZZZZZZZZ";
            WR_TB <= '0'; -- No write
            OE_TB <= '1'; -- Output data from RAM
            wait for T;
            Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
            
            -- Test Reset
            wait for T;
            R_TB <= '1'; -- Reset
            AD_TB <= "ZZZZZZZZZZZZZZZZ";
            wait for T;
            Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
            
            wait;      
        end process;
end architecture;