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我正在为 Verilog 中的课程分配构建单周期处理器，但我的测试台似乎无法获得正确的输出。我已经正确连接了所有东西，并且它在我的测试台的前半部分产生了零，但是一旦我开始输入数据，它就会保持为零。所以我知道我的重置和时钟工作，但是在写部分的某个地方，我忽略了一些东西。我可以用一双新的眼睛，任何帮助表示赞赏。TIA。

注册文件.v：

module registerfile(read1, read2, writeto, writedat, writeenable, out1, out2, clock, reset);

input [4:0] read1;
input [4:0] read2;
input [4:0] writeto;
input [31:0] writedat;
input writeenable, clock, reset;

output [31:0] out1, out2;
// 32 bit registers x 32

reg [31:0] RF[31:0];
reg [31:0] out1;
reg [31:0] out2;

integer i;

always @(posedge reset)
begin
    for (i = 0; i < 32; i++)
        RF[i] <= 0;
    out1 <= 32'h00000000;
    out2 <= 32'h00000000;
end

always @(posedge clock)
begin
    if (writeenable)
        RF[writeto] <= writedat;

    out1 <= RF[read1];
    out2 <= RF[read2];
end

endmodule

RegisterFile_tb.v:

module registerfile_tb ();

reg [4:0] read1;
reg [4:0] read2;
wire [31:0] out1;
wire [31:0] out2;
reg [4:0] writeto;
reg [31:0] writedat;
reg writeenable;
reg clock;
reg reset;

registerfile DUT(read1, read2, writeto, writedat, writeenable, out1, out2, clock, reset);

initial
begin
    clock <= 1;
    reset <= 1;
    #21 reset <= 0;
    #100;

    read1 <= 5'b0;
    read2 <= 5'b0;
    writeto <= 5'b00101;
    writedat <= 32'd0;
    writeenable <= 1;

    #100;
    #21 read1 <= 5'b11010;
    #21 read2 <= 5'b00101;
    #21 read1 <= 5'b00001;
    #21 writedat <= 32'd1; //
    #21 read2 <= 5'b11111;
    #21 read1 <= 5'b01010;
    #21 read2 <= 5'b01110;
end

always @(read1 or read2)
    #21 $display("| read1 = %d | read2 = %d | out1 = %d | out2 = %d |", read1, read2, out1, out2);

endmodule
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1 回答 1

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你的时钟没有切换。您的测试台中应该有一个always #10 clk = !clk;（您可能需要不同的延迟）。

您的显示声明有点奇怪。考虑将其更改为监视器并将其移动到初始块的顶部附近。

供参考。您的代码不会合成。对我来说，可以综合一个寄存器必须只分配一个 always 块。您有单独的时钟块和复位块。要进行异步复位，请使用以下结构。对于同步复位（大多数 FPGA 需要），然后省略or posedge reset

always @(posedge clock or posedge reset)
begin
    if (reset) begin
        for (i = 0; i < 32; i++)
            RF[i] <= 0;
        out1 <= 32'h00000000;
        out2 <= 32'h00000000;
    end
    else begin
        if (writeenable)
            RF[writeto] <= writedat;
        out1 <= RF[read1];
        out2 <= RF[read2];
    end
end
于 2019-03-30T04:35:28.633 回答