concurrency - VHDL中带有向量的并发信号分配

Question

我正在尝试使用 GHDL 编译此代码，但出现错误：'=>' is expected而不是'not'。我希望代码没有任何进程，也没有隐式进程。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY decoder IS PORT 
    (c, b, a, g : IN std_logic;
    y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;

ARCHITECTURE beh_decoder OF decoder IS
BEGIN
    y <= "10000000" WHEN (g NOT (a AND b AND c)) ELSE
         "01000000" WHEN ((a AND g) NOT (b AND c)) ELSE
         "00100000" WHEN ((b AND g) NOT (a AND c)) ELSE
         "00010000" WHEN ((a AND b AND g) NOT c) ELSE
         "00001000" WHEN ((c AND g) NOT (a AND b)) ELSE
         "00000100" WHEN ((a AND c AND g) NOT b) ELSE
         "00000010" WHEN ((b AND c AND g) NOT a) ELSE
         "00000001" WHEN ((a AND g) NOT (b AND c)) ELSE
         "00000000";
END ARCHITECTURE beh_decoder;

Answer 1

when 表达式使用非门作为多输入门。

g NOT (a AND b AND c)

如果我们替换 Q = (a AND b AND c) 你有

g NOT Q

哪个没有意义？并且可能是 GHDL 抱怨的内容。

你想要吗

g OR NOT (a AND b AND c)

或者

g AND NOT (a AND b AND c)

根据您的评论，新代码可能如下所示。您将需要确认逻辑，但它应该可以编译。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY decoder IS PORT 
    (c, b, a, g : IN std_logic;
    y : OUT std_logic_vector(7 DOWNTO 0));
END decoder;

ARCHITECTURE beh_decoder OF decoder IS
BEGIN
    y <= "10000000" WHEN (g AND NOT (a AND b AND c)) ELSE
         "01000000" WHEN ((a AND g) AND NOT (b AND c)) ELSE
         "00100000" WHEN ((b AND g) AND NOT (a AND c)) ELSE
         "00010000" WHEN ((a AND b AND g) AND NOT c) ELSE
         "00001000" WHEN ((c AND g) AND NOT (a AND b)) ELSE
         "00000100" WHEN ((a AND c AND g) AND NOT b) ELSE
         "00000010" WHEN ((b AND c AND g) AND NOT a) ELSE
         "00000001" WHEN ((a AND g) AND NOT (b AND c)) ELSE
         "00000000";
END ARCHITECTURE beh_decoder;